Management and Protection of High-Voltage Direct Current Systems Based on Modular Multilevel Converters

The electrical grid is undergoing large changes due to the massive integration of renewable energy systems and the electrification of transport and heating sectors. These new resources are typically non-dispatchable and dependent on external factors (e.g., weather, user patterns). These two aspects make the generation and demand less predictable, facilitating a larger power variability. As a consequence, rejecting disturbances and respecting power quality constraints gets more challenging, as small power imbalances can create large frequency deviations with faster transients. In order to deal with these challenges, the energy system needs an upgraded infrastructure and improved control system. In this regard, high-voltage direct current (HVdc) systems can increase the controllability of the power system, facilitating the integration of large renewable energy systems. This thesis contributes to the advancement of the state of the art in HVdc systems, addressing the modeling, control and protection of HVdc systems, adopting modular multilevel converter (MMC) technology, with focus in providing services to ac systems. HVdc system control and protection studies need for an accurate HVdc terminal modeling in largely different time frames. Thus, as a first step, this thesis presents a guideline for the necessary level of deepness of the power electronics modeling with respect to the power system problem under study. Starting from a proper modeling for power system studies, this thesis proposes an HVdc frequency regulation approach, which adapts the power consumption of voltage-dependent loads by means of controlled reactive power injections, that control the voltage in the grid. This solution enables a fast and accurate load power control, able to minimize the frequency swing in asynchronous or embedded HVdc applications. One key challenge of HVdc systems is a proper protection system and particularly dc circuit breaker (CB) design, which necessitates fault current analysis for a large number of grid scenarios and parameters. This thesis applies the knowledge developed in the modeling and control of HVdc systems, to develop a fast and accurate fault current estimation method for MMC-based HVdc system. This method, including the HVdc control, achieved to accurately estimate the fault current peak value and slope with very small computational effort compared to the conventional approach using EMT-simulations. This work is concluded introducing a new protection methodology, that involves the fault blocking capability of MMCs with mixed submodule (SM) structure, without the need for an additional CB. The main focus is the adaption of the MMC topology with reduced number of bipolar SM to achieve similar fault clearing performance as with dc CB and tolerable SM over-voltage

Modular Multilevel Converter Based High Voltage DC Protection

This thesis addresses the protection of a high voltage DC (HVDC) system that utilizes the modular multilevel converter (MMC) topology, a voltage sourced converter (VSC), and incorporates two transmission line sections, a cable and an overhead line. Protection for high voltage AC systems is mature in installation experience. On the other hand there are many avenues of research needs for the protection of the more modern technology, HVDC. The avenue of system protection focused upon in this work is the system restart sequence post DC side faults. This restart sequence is simply the sequence of events that occur necessarily in order to restart the HVDC system after a specified fault is already isolated and diminished. This avenue of system protection is focused upon but not exclusively. Fault isolation and suppression are also protection topics noted and discussed. Ultimately a fault section identification protection method is required for restart of the HVDC system when there are two transmission line sections. Specific to the HVDC system design presented there is desire for no communication channel between the converter stations of the system. Additionally, recovery of the system to normal operation is preferably as fast as possible in order to maintain power delivery with minimal disturbance. Solutions to these challenges are investigated and proposed. The first part of this thesis work involves the detailed modeling of the MMC-HVDC system in the PSCAD simulation environment. After providing the validation of the model, both a parameter sensitivity analysis and an in-depth fault case analysis are performed for the overall examination of protection needs of the HVDC design. The fault analysis evaluation brings to light the means for a unique protection coordination method for the system design during post-fault system restart. The protection method ensures that cable faults, assumed to be permanent faults, are not reclosed upon while for any non-permanent faults attempt of reclose is made. The protection coordination method proposed in this work is unique in that it utilizes a signal characteristic to the HVDC system design to implement protection coordination without the use of a communications channel between converter stations

Fault discrimination and protection coordination for a bipolar full-bridge MMC-HVDC scheme

Fault discrimination and protection design for bipolar high-voltage direct current transmission solutions based on modular multilevel converters (MMC-HVDC) links are of significant importance for a reliable and resilient power transmission. If full-bridge submodules are utilised, fault-dependent handling concepts considering the location of an event are enabled. This study presents a comprehensive approach to differentiate and deal with internal converter and dc side faults. While a multitude of measurements inside and at the clamps of each converter is usually only used for simple threshold-based hardware-related protection, additional differential and derivative criteria may further improve selectivity. However, this requires careful configuration to avoid improper reactions. To highlight the coordinated manner of the proposed concept, various faults are analysed and selected examples are explicitly investigated and visualised using the PSCAD EMTDC software

A New MMC Topology Which Decreases the Sub Module Voltage Fluctuations at Lower Switching Frequencies and Improves Converter Efficiency

Modular Multi-level inverters (MMCs) are becoming more common because of their suitability for applications in smart grids and multi-terminal HVDC transmission networks. The comparative study between the two classic topologies of MMC (AC side cascaded and DC side cascaded topologies) indicates some disadvantages which can affect their performance. The sub module voltage ripple and switching losses are one of the main issues and the reason for the appearance of the circulating current is sub module capacitor voltage ripple. Hence, the sub module capacitor needs to be large enough to constrain the voltage ripple when operating at lower switching frequencies. However, this is prohibitively uneconomical for the high voltage applications. There is always a trade off in MMC design between the switching frequency and sub module voltage ripple

High Power Density and High Efficiency Converter Topologies for Renewable Energy Conversion and EV Applications

This dissertation work presents two novel converter topologies (a three-level ANPC inverter utilizing hybrid Si/SiC switches and an Asymmetric Alternate Arm Converter (AAAC) topology) that are suitable for high efficiency and high-power density energy conversion systems. The operation principle, modulation, and control strategy of these newly introduced converter topologies are presented in detail supported by simulation and experimental results. A thorough design optimization of these converter topologies (Si/SiC current rating ratio optimization and gate control strategies for the three-level ANPC inverter topology and component sizing for the asymmetric alternate arm converter topology) are also presented. Performance comparison of the proposed converter topologies with other similar converter topologies is also presented. The performance of the proposed ANPC inverter topology is compared with other ANPC inverter topologies such as an all SiC MOSFET ANPC inverter topology, an all Si IGBT ANPC inverter topology and mixed Si IGBT and SiC MOSFET based ANPC inverter topologies in terms of efficiency and cost. The efficiency and cost comparison results show that the proposed hybrid Si/SiC switch based ANPC inverter has higher efficiency and lower cost compared to the other ANPC inverter topologies considered for the comparison. The performance of the asymmetric alternate arm converter topology is also compared with other similar voltage source converter topologies such as the modular multilevel converter topology, the alternate arm converter topology, and the improved alternate arm converter topology in terms of total device count, number of switches per current conduction path, output voltage levels, dc-fault blocking capability and overmodulation capability. The proposed multilevel converter topology has lower total number of devices and lower number of devices per current conduction path hence it has lower cost and lower conduction power loss. However, it has lower number of output voltage levels (requiring larger ac interface inductors) and lacks dc-fault blocking and overmodulation operation capabilities. A converter figure-of-merit accounting for the hybrid Si/SiC switch and converter topology properties is also proposed to help perform quick performance comparison between different hybrid Si/SiC switch based converter topologies. It eliminates the need for developing full electro-thermal power loss model for different converter topologies that would otherwise be needed to carry out power loss comparison between different converter topologies. Hence it saves time and effort