Fast motion estimation algorithm in H.264 standard

In H.264/AVC standard, the block motion estimation pattern is used to estimate the motion which is a very time consuming part. Although many fast algorithms have been proposed to reduce the huge calculation, the motion estimation time still cannot achieve the critical real time application. So to develop an algorithm which will be fast and having low complexity became a challenge in this standard.For this reasons, a lot of block motion estimation algorithms have been proposed. Typically the block motion estimation part is categorized into two parts. (1) Single pixel motion estimation (2) Fractional pixel motion estimation. In single pixel motion estimation one kind of fast motion algorithm uses fixed pattern like Three Step search, 2-D Logarithmic Search. Four Step search,Diamond Search, Hexagon Based Search. These algorithms are able to reduce the search point and get good coding quality. But the coding quality decreases when the fixed pattern does not fit the real life video sequence. In this thesis we tried to reduce the time complexity and number of search point by using an early termination method which is called adaptive threshold selection. We have used this method in three step search (TSS) and four step search and compared the performance with already existing block matching algorithm.This thesis work proposes fast sub-pixel motion estimation techniques having lower computational complexity. The proposed methods are based on mathematical models of the motion compensated prediction errors in compressing moving pictures. Unlike conventional hierarchical motion estimation techniques, the proposed methods avoid sub-pixel interpolation and subsequent secondary search after the integer-precision motion estimation, resulting in reduced computational time. In order to decide the coefficients of the models, the motion-compensated prediction errors of the neighboring pixels around the integer-pixel motion vector are utilized

Wyner-Ziv side information generation using a higher order piecewise trajectory temporal interpolation algorithm

Distributed video coding (DVC) reverses the traditional coding paradigm of complex encoders allied with basic decoding, to one where the computational cost is largely incurred by the decoder. This enables low-cost, resource-poor sensors to be used at the transmitter in various applications including multi-sensor surveillance. A key constraint governing DVC performance is the quality of side information (SI), a coarse representation of original video frames which are not available at the decoder. Techniques to generate SI have generally been based on linear temporal interpolation, though these do not always produce satisfactory SI quality especially in sequences exhibiting asymmetric (non-linear) motion. This paper presents a higher-order piecewise trajectory temporal interpolation (HOPTTI) algorithm for SI generation that quantitatively and perceptually affords better SI quality in comparison to existing temporal interpolation-based approaches

Implementing video compression algorithms on reconfigurable devices

The increasing density offered by Field Programmable Gate Arrays(FPGA), coupled with their short design cycle, has made them a popular choice for implementing a wide range of algorithms and complete systems. In this thesis the implementation of video compression algorithms on FPGAs is studied. Two areas are specifically focused on; the integration of a video encoder into a complete system and the power consumption of FPGA based video encoders. Two FPGA based video compression systems are described, one which targets surveillance applications and one which targets video conferencing applications. The FPGA video surveillance system makes use of a novel memory format to improve the efficiency with which input video sequences can be loaded over the system bus. The power consumption of a FPGA video encoder is analyzed. The results indicating that the motion estimation encoder stage requires the most power consumption. An algorithm, which reuses the intra prediction results generated during the encoding process, is then proposed to reduce the power consumed on an FPGA video encoder’s external memory bus. Finally, the power reduction algorithm is implemented within an FPGA video encoder. Results are given showing that, in addition to reducing power on the external memory bus, the algorithm also reduces power in the motion estimation stage of a FPGA based video encoder

Optimization of the motion estimation for parallel embedded systems in the context of new video standards

15 pagesInternational audienceThe effciency of video compression methods mainly depends on the motion compensation stage, and the design of effcient motion estimation techniques is still an important issue. An highly accurate motion estimation can significantly reduce the bit-rate, but involves a high computational complexity. This is particularly true for new generations of video compression standards, MPEG AVC and HEVC, which involves techniques such as different reference frames, sub-pixel estimation, variable block sizes. In this context, the design of fast motion estimation solutions is necessary, and can concerned two linked aspects: a high quality algorithm and its effcient implementation. This paper summarizes our main contributions in this domain. In particular, we first present the HME (Hierarchical Motion Estimation) technique. It is based on a multi-level refinement process where the motion estimation vectors are first estimated on a sub-sampled image. The multi-levels decomposition provides robust predictions and is particularly suited for variable block sizes motion estimations. The HME method has been integrated in a AVC encoder, and we propose a parallel implementation of this technique, with the motion estimation at pixel level performed by a DSP processor, and the sub-pixel refinement realized in an FPGA. The second technique that we present is called HDS for Hierarchical Diamond Search. It combines the multi-level refinement of HME, with a fast search at pixel-accuracy inspired by the EPZS method. This paper also presents its parallel implementation onto a multi-DSP platform and the its use in the HEVC context

Fast Motion Estimation Algorithms for Block-Based Video Coding Encoders

The objective of my research is reducing the complexity of video coding standards in real-time scalable and multi-view applications

Low complexity hardware oriented H.264/AVC motion estimation algorithm and related low power and low cost architecture design

制度:新 ; 報告番号:甲2999号 ; 学位の種類:博士(工学) ; 授与年月日:2010/3/15 ; 早大学位記番号:新525