Analytical model of nanowire FETs in a partially ballistic or dissipative transport regime

The intermediate transport regime in nanoscale transistors between the fully ballistic case and the quasi equilibrium case described by the drift-diffusion model is still an open modeling issue. Analytical approaches to the problem have been proposed, based on the introduction of a backscattering coefficient, or numerical approaches consisting in the MonteCarlo solution of the Boltzmann transport equation or in the introduction of dissipation in quantum transport descriptions. In this paper we propose a very simple analytical model to seamlessly cover the whole range of transport regimes in generic quasi-one dimensional field-effect transistors, and apply it to silicon nanowire transistors. The model is based on describing a generic transistor as a chain of ballistic nanowire transistors in series, or as the series of a ballistic transistor and a drift-diffusion transistor operating in the triode region. As an additional result, we find a relation between the mobility and the mean free path, that has deep consequences on the understanding of transport in nanoscale devices

Compact modeling of the rf and noise behavior of multiple-gate mosfets

La reducción de la tecnología MOSFET planar ha sido la opción tecnológica dominante en las últimas décadas. Sin embargo, hemos llegado a un punto en el que los materiales y problemas en los dispositivos surgen, abriendo la puerta para estructuras alternativas de los dispositivos. Entre estas estructuras se encuentran los dispositivos DG, SGT y Triple-Gate. Estas tres estructuras están estudiadas en esta tesis, en el contexto de rducir las dimensiones de los dispositivos a tamaños tales que los mecanismos cuánticos y efectos de calan coro deben tenerse n cuenta. Estos efectos vienen con una seria de desafíos desde el pun to de vista de modelación, unos de los más grandes siendo el tiempo y los recursos comprometidos para ejecutar las simulaciones. para resolver este problema, esta tesis propone modelos comlets analíticos y compactos para cada una de las geometrías, validos desde DC hasta el modo de operación en Rf para los nodos tecnológicos futuros. Dichos modelos se han extendido para analizar el ruido de alta frecuencia en estos diapositivos

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Green's functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed

Compact Models for Integrated Circuit Design

This modern treatise on compact models for circuit computer-aided design (CAD) presents industry standard models for bipolar-junction transistors (BJTs), metal-oxide-semiconductor (MOS) field-effect-transistors (FETs), FinFETs, and tunnel field-effect transistors (TFETs), along with statistical MOS models. Featuring exercise problems at the end of each chapter and extensive references at the end of the book, the text supplies fundamental and practical knowledge necessary for efficient integrated circuit (IC) design using nanoscale devices. It ensures even those unfamiliar with semiconductor physics gain a solid grasp of compact modeling concepts

ランダム・テレグラフ・ノイズの微細MOSFETへの影響に関する研究

筑波大学 (University of Tsukuba)201

Characterization and modeling of low-frequency noise in Hf-based high -kappa dielectrics for future cmos applications

The International Technology Roadmap for Semiconductors outlines the need for high-K dielectric based gate-oxide Metal Oxide Semiconductor Field Effect Transistors for sub-45 nm technology nodes. Gate oxides of hafnium seem to be the nearest and best alternative for silicon dioxide, when material, thermal and structural properties are considered. Usage of poly-Si as a gate electrode material degrades the performance of the device and hence gate stacks based on metal gate electrodes are gaining high interest. Though a substantial improvement in the performance has been achieved with these changes, reliability issues are a cause of concern. For analog and mixed-signal applications, low-frequency (I /f~ noise is a major reliability factor. Also in recent years. low frequency noise diagnostics has become a powerful tool for device performance and reliability characterization. This dissertation work demonstrates the necessity of gate stack engineering for achieving a low I/f noise performance. Changes in the material and process parameters of the devices, impact the 1/f noise behavior. The impact of 1/f noise on gate technology and processing parameters xvere identified and investigated. The thickness and the quality of the interfacial oxide, the nitridation effects of the layers, high-K oxide, bulk properties of the high-K layer. percentage of hafnium content in the high-K, post deposition anneal (PDA) treatments, effects of gate electrode material (poly-silicon. fully silicided or metal). Gate electrode processing are investigated in detail. The role of additional interfaces and bulk layers of the gate stack is understood. The dependence of low-frequency noise on high and low temperatures was also investigated. A systematic and a deeper understanding of these parameters on 1/f noise behavior are deduced which also forms the basis for improved physics-based 1/f noise modeling. The model considers the effect of the interfacial layer and also temperature, based on tunneling based thermally activated model. The simulation results of improved drain-current noise model agree well with the experimentally calculated values

Caractérisation électrique et modélisation des transistors FDSOI sub-22nm

Silicon on insulator (SOI) transistors are among the best candidates for sub-22nm technology nodes. At this scale, the devices integrate extremely thin buried oxide layers (BOX) and body. They also integrate advanced high-k dielectric / metal gate stacks and strain engineering is used to improve transport properties with, for instance, the use of SiGe alloys in the channel of p-type MOS transistors. The optimization of such a technology requires precise and non-destructive experimental techniques able to provide information about the quality of electron transport and interface quality, as well as about the real values of physical parameters (dimensions and doping level) at the end of the process. Techniques for parameter extraction from electrical characteristics have been developed over time. The aim of this thesis work is to reconsider these methods and to further develop them to account for the extremely small dimensions used for sub-22nm SOI generations. The work is based on extended characterization and modelling in support. Among the original results obtained during this thesis, special notice should be put on the adaptation of the complete split CV method which is now able to extract the characteristic parameters for the entire stack, from the substrate and its doping level to the gate stack, as well as an extremely detailed analysis of electron transport based on low temperature characterization in back-gate electrostatic coupling conditions or the exploitation of channel magnetoresistance from the linear regime of operation to saturation. Finally, a detailed analysis of low-frequency noise closes this study.Parmi les architectures candidates pour les générations sub-22nm figurent les transistors sur silicium sur isolant (SOI). A cette échelle, les composants doivent intégrer des films isolants enterrés (BOX) et des canaux de conduction (Body) ultra-minces. A ceci s'ajoute l'utilisation d'empilements de grille avancés (diélectriques à haute permittivité / métal de grille) et une ingénierie de la contrainte mécanique avec l'utilisation d'alliages SiGe pour le canal des transistors de type P. La mise au point d'une telle technologie demande qu'on soit capable d'extraire de façon non destructive et avec précision la qualité du transport électronique et des interfaces, ainsi que les valeurs des paramètres physiques (dimensions et dopages), qui sont obtenues effectivement en fin de fabrication. Des techniques d'extraction de paramètres ont été développées au cours du temps. L'objectif de cette thèse est de reconsidérer et de faire évoluer ces techniques pour les adapter aux épaisseurs extrêmement réduites des composants étudiés. Elle combine mesures approfondies et modélisation en support. Parmi les résultats originaux obtenus au cours de cette thèse, citons notamment l'adaptation de la méthode split CV complète qui permet désormais d'extraire les paramètres caractérisant l'ensemble de l'empilement SOI, depuis le substrat et son dopage jusqu'à la grille, ainsi qu'une analyse extrêmement détaillée du transport grâce à des mesures en régime de couplage grille arrière à température variable ou l'exploitation de la magnétorésistance de canal depuis le régime linéaire jusqu'en saturation. Le mémoire se termine par une analyse détaillée du bruit basse fréquence

Low-frequency noise in downscaled silicon transistors: Trends, theory and practice

By the continuing downscaling of sub-micron transistors in the range of few to one deca-nanometers, we focus on the increasing relative level of the low-frequency noise in these devices. Large amount of published data and models are reviewed and summarized, in order to capture the state-of-the-art, and to observe that the 1/area scaling of low-frequency noise holds even for carbon nanotube devices, but the noise becomes too large in order to have fully deterministic devices with area less than 10nm×10nm. The low-frequency noise models are discussed from the point of view that the noise can be both intrinsic and coupled to the charge transport in the devices, which provided a coherent picture, and more interestingly, showed that the models converge each to other, despite the many issues that one can find for the physical origin of each model. Several derivations are made to explain crossovers in noise spectra, variable random telegraph amplitudes, duality between energy and distance of charge traps, behaviors and trends for figures of merit by device downscaling, practical constraints for micropower amplifiers and dependence of phase noise on the harmonics in the oscillation signal, uncertainty and techniques of averaging by noise characterization. We have also shown how the unavoidable statistical variations by fabrication is embedded in the devices as a spatial “frozen noise”, which also follows 1/area scaling law and limits the production yield, from one side, and from other side, the “frozen noise” contributes generically to temporal 1/f noise by randomly probing the embedded variations during device operation, owing to the purely statistical accumulation of variance that follows from cause-consequence principle, and irrespectively of the actual physical process. The accumulation of variance is known as statistics of “innovation variance”, which explains the nearly log-normal distributions in the values for low-frequency noise parameters gathered from different devices, bias and other conditions, thus, the origin of geometric averaging in low-frequency noise characterizations. At present, the many models generally coincide each with other, and what makes the difference, are the values, which, however, scatter prominently in nanodevices. Perhaps, one should make some changes in the approach to the low-frequency noise in electronic devices, to emphasize the “statistics behind the numbers”, because the general physical assumptions in each model always fail at some point by the device downscaling, but irrespectively of that, the statistics works, since the low-frequency noise scales consistently with the 1/area law

Caractérisation, mécanismes et applications mémoire des transistors avancés sur SOI

Ce travail présente les principaux résultats obtenus avec une large gamme de dispositifs SOI avancés, candidats très prometteurs pour les futurs générations de transistors MOSFETs. Leurs propriétés électriques ont été analysées par des mesures systématiques, agrémentées par des modèles analytiques et/ou des simulations numériques. Nous avons également proposé une utilisation originale de dispositifs FinFETs fabriqués sur ONO enterré en fonctionnalisant le ONO à des fins d'application mémoire non volatile, volatile et unifiées. Après une introduction sur l'état de l'art des dispositifs avancés en technologie SOI, le deuxième chapitre a été consacré à la caractérisation détaillée des propriétés de dispositifs SOI planaires ultra- mince (épaisseur en dessous de 7 nm) et multi-grille. Nous avons montré l excellent contrôle électrostatique par la grille dans les transistors très courts ainsi que des effets intéressants de transport et de couplage. Une approche similaire a été utilisée pour étudier et comparer des dispositifs FinFETs à double grille et triple grille. Nous avons démontré que la configuration FinFET double grille améliore le couplage avec la grille arrière, phénomène important pour des applications à tension de seuil multiple. Nous avons proposé des modèles originaux expliquant l'effet de couplage 3D et le comportement de la mobilité dans des TFTs nanocristallin ZnO. Nos résultats ont souligné les similitudes et les différences entre les transistors SOI et à base de ZnO. Des mesures à basse température et de nouvelles méthodes d'extraction ont permis d'établir que la mobilité dans le ZnO et la qualité de l'interface ZnO/SiO2 sont remarquables. Cet état de fait ouvre des perspectives intéressantes pour l'utilisation de ce type de matériaux aux applications innovantes de l'électronique flexible. Dans le troisième chapitre, nous nous sommes concentrés sur le comportement de la mobilité dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnétorésistance à basse température. Nous avons mis en évidence expérimentalement un comportement de mobilité inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre résultat original concerne l existence et l interprétation de la magnétorésistance géométrique dans les FinFETs.L'utilisation de FinFETs fabriqués sur ONO enterré en tant que mémoire non volatile flash a été proposée dans le quatrième chapitre. Deux mécanismes d'injection de charge ont été étudiés systématiquement. En plus de la démonstration de la pertinence de ce type mémoire en termes de performances (rétention, marge de détection), nous avons mis en évidence un comportement inattendu : l amélioration de la marge de détection pour des dispositifs à canaux courts. Notre concept innovant de FinFlash sur ONO enterré présente plusieurs avantages: (i) opération double-bit et (ii) séparation de la grille de stockage et de l'interface de lecture augmentant la fiabilité et autorisant une miniaturisation plus poussée que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons exploré le concept de mémoire unifiée, en combinant les opérations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterré. Comme escompté pour les mémoires dites unifiées, le courant transitoire en mode 1T-DRAM dépend des charges non volatiles stockées dans le ONO. D'autre part, nous avons montré que les charges piégées dans le nitrure ne sont pas perturbées par les opérations de programmation et lecture de la 1T-DRAM. Les performances de cette mémoire unifiée multi-bits sont prometteuses et pourront être considérablement améliorées par optimisation technologique de ce dispositif.The evolution of electronic systems and portable devices requires innovation in both circuit design and transistor architecture. During last fifty years, the main issue in MOS transistor has been the gate length scaling down. The reduction of power consumption together with the co-integration of different functions is a more recent avenue. In bulk-Si planar technology, device shrinking seems to arrive at the end due to the multiplication of parasitic effects. The relay has been taken by novel SOI-like device architectures. In this perspective, this manuscript presents the main achievements of our work obtained with a variety of advanced fully depleted SOI MOSFETs, which are very promising candidates for next generation MOSFETs. Their electrical properties have been analyzed by systematic measurements and clarified by analytical models and/or simulations. Ultimately, appropriate applications have been proposed based on their beneficial features.In the first chapter, we briefly addressed the short-channel effects and the diverse technologies to improve device performance. The second chapter was dedicated to the detailed characterization and interesting properties of SOI devices. We have demonstrated excellent gate control and high performance in ultra-thin FD SOI MOSFET. The SCEs are efficiently suppressed by decreasing the body thickness below 7 nm. We have investigated the transport and electrostatic properties as well as the coupling mechanisms. The strong impact of body thickness and temperature range has been outlined. A similar approach was used to investigate and compare vertical double-gate and triple-gate FinFETs. DG FinFETs show enhanced coupling to back-gate bias which is applicable and suitable for dynamic threshold voltage tuning. We have proposed original models explaining the 3D coupling effect in FinFETs and the mobility behavior in ZnO TFTs. Our results pointed on the similarities and differences in SOI and ZnO transistors. According to our low-temperature measurements and new promoted extraction methods, the mobility in ZnO and the quality of ZnO/SiO2 interface are respectable, enabling innovating applications in flexible, transparent and power electronics. In the third chapter, we focused on the mobility behavior in planar SOI and FinFET devices by performing low-temperature magnetoresistance measurements. Unusual mobility curve with multi-branch aspect were obtained when two or more channels coexist and interplay. Another original result in the existence of the geometrical magnetoresistance in triple-gate and even double-gate FinFETs.The operation of a flash memory in FinFETs with ONO buried layer was explored in the forth chapter. Two charge injection mechanisms were proposed and systematically investigated. We have discussed the role of device geometry and temperature. Our novel ONO FinFlash concept has several distinct advantages: double-bit operation, separation of storage medium and reading interface, reliability and scalability. In the final chapter, we explored the avenue of unified memory, by combining nonvolatile and 1T-DRAM operations in a single transistor. The key result is that the transient current, relevant for 1T-DRAM operation, depends on the nonvolatile charges stored in the nitride buried layer. On the other hand, the trapped charges are not disturbed by the 1T-DRAM operation. Our experimental data offers the proof-of-concept for such advanced memory. The performance of the unified/multi-bit memory is already decent but will greatly improve in the coming years by processing dedicated devices.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Realisation of III-V Tunnel-FET with in-situ ultimate scaled gate stack for high performance power efficient CMOS

The main objective of this thesis is realising a non-planar III-V Tunnel-FET for low power device applications. The differentiating aspect of this work is based around clustered inductively coupled plasma (ICP) etch and atomic layer deposition (ALD) tools. This approach was intended to mitigate native oxide formation on etched III-V surfaces prior to gate stack deposition by ALD. The use of a cluster tool also offers the benefit of cleaning III-V surfaces “in-situ” using low damage plasma based approaches. In addition, activity on scaling the equivalent oxide thickness of the gate stack and evaluating different heterostructures are explored in this work for the realisation of high performance TunnelFET. Initially, gate stacks on both p- and n- (110)-oriented In0.53Ga0.47As were examined to understand the basic electrical properties of these interfaces, important for non-planar device architectures. An optimised process, based on ex-situ sulphur-based passivation before ALD of gate dielectrics, and forming gas annealing (FGA) after gate metal deposition, is demonstrated for the first time to show significant Fermi level movement through the bandgap. Quantitatively, interface state density (Dit) values in the range of 0.87-1.8 × 1012 cm-2eV-1 around the midgap energy level were obtained. The lowest Dit value is estimated to be 3.1 × 1012 cm-2eV-1 close to the conduction band edge showing the combination of sulphur passivation and (FGA) is effective is passivating the trap states in the upper half of the bandgap on Al2O3/In0.53Ga0.47As (110) MOSCAPs. Furthermore, by analysis of CV hysteresis biasing at 1.1 V beyond the flatband voltage, the border trap density on n-type MOSCAPs was observed to reduce, after FGA from 1.8 × 1012 cm-2 to 5.3 × 1011 cm-2. The result observed in p-type MOSCAPs is in contrast, with increasing border trap density from 7.3 × 1011 cm-2 to 1.4 × 1012 cm-2 under the similar bias condition, i.e. the FGA process is not as effective in passivating states close to the valence band. In addition, the analysis undertaken in this thesis determined the value of the conduction band offset at the Al2O3/In0.53Ga0.47As (110) to be is 1.81eV – the first report of this parameter. The non-planar devices of this work also require low damage etching processes for fin/wire formation. Therefore, the performance of in-situ deposited gate stacks to In0.53Ga0.47As (100)- and (110)-oriented substrates which had been subjected to a CH4/Cl2/H2 based ICP etch chemistry, which forms vertical InGaAs sidewall profiles, were assessed. Based on CV and IV, and X-ray Photo-Spectroscopy (XPS) spectral analyses, the performance of gate stacks deposited on (110)-oriented In0.53Ga0.47As subjected to a ICP dry etch suffers more damage compared to gate stacks on (100)-oriented In0.53Ga0.47As. To minimise the etching damage, cyclic TMA/plasma gas pretreatment prior to ALD is introduced on both (100)- and (110)-oriented surfaces. The interface trap density of gate stacks on (110)-oriented In0.53Ga0.47As with TMA/H2 gas pre-treatment improves from 6 × 1011 cm-2eV-1 to 2.8 × 1011 cm-2eV-1 close to the conduction band edge. Based on this in-situ gate stack process, a gate stack with reduced capacitor equivalent thickness (CET) on both (100) and (110) oriented surfaces are achieved by using a TiN layer deposited in-situ by ALD before ex-situ gate metal deposition. The lowest CET was around 1.09 nm for a HfO2/TiN stack deposited on (100)-oriented In0.53Ga0.47As. This optimised gate stack was included in an InGaAs-based tunnel-FET process flow using p-n, p-i-n, and p-n-i-n heterostructures. Comparing with p-n Tunnel-FETs, the pi-n structure provides better electrical characteristics for In0.53Ga0.47As with a subthreshold swing (SS) of 120 mV/dec at the condition of VDS = 0.05V. The peak transconductance peak of the p-i-n Tunnel-FET at the condition of VDS = 0.3V is around 6 uS/um. Next, an inserted n-pocket p-n-i-n Tunnel-FET was studied. In addition to providing comparable on current with the p-i-n Tunnel-FET of 1.1 uA/um at the bias condition of VDS = 300mV, the subthreshold swing of the p-n-i-n devices improves by 46% due to the lower leakage floor from the n-pocket layer incorporation. Most importantly, the non-planar configuration of the p-n-i-n Tunnel-FET improves both the SS and on-current to 152 mV/dec at the bias condition of VDS = 300mV and 1.3 uA/um at the bias condition of VDS = 500mV and VGS = 900mV, respectively. Above these aspects and benchmark, all this data implies that a non-planar p-n-i-n InGaAs TunnelFET is a promising candidate for future generations of low power applications