A framework for fine-grain synthesis optimization of operational amplifiers

This thesis presents a cell-level framework for Operational Amplifiers Synthesis (OASYN) coupling both circuit design and layout. For circuit design, the tool applies a corner-driven optimization, accounting for on-chip performance variations. By exploring the process, voltage, and temperature variations space, the tool extracts design worst case solution. The tool undergoes sensitivity analysis along with Pareto-optimality to achieve required specifications. For layout phase, OASYN generates a DRC proved automated layout based on a sized circuit-level description. Morata et al. (1996) introduced an elegant representation of block placement called sequence pair for general floorplans (SP). Like TCG and BSG, but unlike O-tree, B*tree, and CBL, SP is P-admissible. Unlike SP, TCG supports incremental update during operation and keeps the information of the boundary modules as well as their relative positions in the representation. Block placement algorithms that are based on SP use heuristic optimization algorithms, e.g., simulated annealing where generation of large number of sequence pairs are required. Therefore a fast algorithm is needed to generate sequence pairs after each solution perturbation. The thesis presents a new simple and efficient O(n) runtime algorithm for fast realization of incremental update for cost evaluation. The algorithm integrates sequence pair and transitive closure graph advantages into TCG-S* a superior topology update scheme which facilitates the search for optimum desired floorplan. Experiments show that TCG-S* is better than existing works in terms of area utilization and convergence speed. Routing-aware placement is implemented in OASYN, handling symmetry constraints, e.g., interdigitization, common centroid, along with congestion elimination and the enhancement of placement routability

Block-matching motion estimation algorithms for video processing and compression: A brief overview

Humanity created different methods for sharing information. One of the first forms of sharing information and knowledge were images. In the beginning, the process of sharing was relying on static appearances. With the invention of moving pictures by Eadweard Muybridge in the first part of 1870s, this exchange and sharing gained a new quality. Now it was possible to show and preserve motion too. Since that time, technology has changed rapidly. The latest discoveries and improvements from the point of view of technology use computer and IT technologies extensively. Today it is possible for everybody to create and record movies by themselves using affordable and convenient technological devices. Also the process of sharing evolved rapidly and become cheaper and cheaper. We are now able to record some movies and share them through the Internet or other carriers in real time or near real time. However, this also creates serious problems due to the huge volume of data to be sent through the data lines. Therefore, research has concentrated on methods to decrease the data volume without losing the quality. One way to do that is to create effective CODECs. A major drawback of moving pictures is the motion itself. CODECs have to minimize the size of videos without paying the price of quality losses but have also to reduce the computational complexity. Both of these requirements can be achieved with a solid knowledge of motion estimation among others. This paper gives a general overview and survey of some existing and important approaches without the claim of having a complete overview of the field

Computer aided design of printed wiring boards

A method is described for the computer-aided layout of printed wiring boards. The type of board considered is a single sided board containing discrete components. The required input for the layout algorithm is coded from the relevant circuit diagram, together with a description of the component dimensions. This information is then stored within the computer in a data structure. The circuit components and their interconnections are represented by a set of nodes and branches. The principles of graph theory are used to construct an abstract model of the layout. A number of the nodes and branches of the circuit are first used in the construction of a planar graph. A method is then described for inserting the remaining branches into the graph to form a "pseudo planar graph". This represents a set of components and conductor paths which can be laid out on a single sided board without intersections. The number of conductor crossings is thus minimised before the actual layout commences. An algorithm is then described for automatically constructing a board layout from the pseudo planar graph. The relative interconnections are already known so the placement of components and routing of conductor paths can proceed simultaneously. The layout is therefore constructed in a series of logical steps working across from one edge of the board to the other. This approach contrasts with the more usual methods of layout in which components are placed first, followed by a search for conductor routes. The layout algorithm is also provided with facilities for man-machine interaction by means of a graphical display and light pen. Interaction allows the user to alter the positions of components during the construction of the layout. Thus the skill and experience of the user can be combined with the speed and accuracy of the automatic algorithm. Interaction also enables special conditions to be incorporated into the layout which would otherwise entail considerable programming effort. Three different circuits are used to test the layout algorithm. The results are shown for layouts constructed both automatically and by the use of interaction. One layout is also compared with a manually-produced layout of the same circuit. The results show that a feasible method has been developed for the layout of printed wiring boards by computer. Comparable results are produced in considerably less time than normal layout methods

High-level power optimisation for Digital Signal Processing in Recon gurable Logic

This thesis is concerned with the optimisation of Digital Signal Processing (DSP) algorithm implementations on recon gurable hardware via the selection of appropriate word-lengths for the signals in these algorithms, in order to minimise system power consumption. Whilst existing word-length optimisation work has concentrated on the minimisation of the area of algorithm implementations, this work introduces the rst set of power consumption models that can be evaluated quickly enough to be used within the search of the enormous design space of multiple word-length optimisation problems. These models achieve their speed by estimating both the power consumed within the arithmetic components of an algorithm and the power in the routing wires that connect these components, using only a high-level description of the algorithm itself. Trading o a small reduction in power model accuracy for a large increase in speed is one of the major contributions of this thesis. In addition to the work on power consumption modelling, this thesis also develops a new technique for selecting the appropriate word-lengths for an algorithm implementation in order to minimise its cost in terms of power (or some other metric for which models are available). The method developed is able to provide tight lower and upper bounds on the optimal cost that can be obtained for a particular word-length optimisation problem and can, as a result, nd provably near-optimal solutions to word-length optimisation problems without resorting to an NP-hard search of the design space. Finally the costs of systems optimised via the proposed technique are compared to those obtainable by word-length optimisation for minimisation of other metrics (such as logic area) and the results compared, providing greater insight into the nature of wordlength optimisation problems and the extent of the improvements obtainable by them

Human pattern nesting strategies in a genetic algorithms framework

Thesis (Sc. D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 1995.Includes bibliographical references (p. 127-129).by Rahul Dighe.Sc.D