Impact of using approximate FP multipliers in a neural network

En els últims anys, computació aproximada ha estat un dels temes més populars en camps com el reconeixement d'imatges, l'anàlisi d'imatges, el processament del llenguatge. Molts científics han estat estudiant com aprofitar l’ús d’unitats aritmètiques aproximades per millorar l'eficiència, reduir el consum d'energia i els retards en implementacions de xarxes neuronals. En aquesta tesi proposem tres multiplicadors aproximats per la multiplicació de les mantisses. El primer està dissenyat per reduir el nombre de càlculs posant una part del resultat a un valor constant determinat. El segon és el multiplicador logarítmic de Mitchell i el tercer és el multiplicador logarítmic amb un carry per compensar l'error negatiu que provoca el multiplicador logarítmic. Per a avaluar aquests tres multiplicadors, utilitzarem la xarxa neuronal YOLOv3, basada en el framework de xarxa neuronal de codi obert que s'anomena Darknet. Aquest framework està dedicat a fer reconeixement d'objectes d'imatges.In the last few years, approximate computing has been one of the most popular topics in fields like image recognition, image analysis, language processing, self- driving, etc. Many scientists have been studying how to make use of approximate arithmetic units to improve the efficiency, reduce the power consumption and delays of neural networks implementation. In this thesis, we proposed three approximate multipliers for the mantissas multiplication, the first one is designed to reduce the number of calculations by putting one segment of the result to ‘1’ s. The second one is the Mitchell logarithmic multiplier and the third one is the logarithmic multiplier with a set-one adder to compensate for the negative error which is brought by the Mitchell multiplier. In order to evaluate these three multipliers, we are going to use YOLOv3, based on the open-source neural network framework which is called Darknet. This framework is dedicated to doing object recognition of images and we obtain the results after each execution

Generation and Analysis of Constrained Random Sampling Patterns

Random sampling is a technique for signal acquisition which is gaining popularity in practical signal processing systems. Nowadays, event-driven analog-to-digital converters make random sampling feasible in practical applications. A process of random sampling is defined by a sampling pattern, which indicates signal sampling points in time. Practical random sampling patterns are constrained by ADC characteristics and application requirements. In this paper authors introduce statistical methods which evaluate random sampling pattern generators with emphasis on practical applications. Furthermore, the authors propose a new random pattern generator which copes with strict practical limitations imposed on patterns, with possibly minimal loss in randomness of sampling. The proposed generator is compared with existing sampling pattern generators using the introduced statistical methods. It is shown that the proposed algorithm generates random sampling patterns dedicated for event-driven-ADCs better than existed sampling pattern generators. Finally, implementation issues of random sampling patterns are discussed.Comment: 29 pages, 12 figures, submitted to Circuits, Systems and Signal Processing journa

Reduction of Near-Field Grating Lobes in Sparse Acoustic Phased Arrays

Acoustic phased arrays with inter-element spacings of greater than one half-wavelength will produce grating lobes that decrease the usefulness of the array. With many array configurations, the near-field and far-field character of these lobes is significantly different -- an optimization of the array configuration to reduce grating lobes in the far-field can have little bearing on the performance of the array in the near-field. The focus of this thesis is the reduction of grating lobes in the near-field by iterative optimization. Genetic algorithms are employed to choose inter-element spacings which are able to reduce the magnitude of grating lobes at select distances in the near-field. The genetic algorithm produced configurations that are theoretically able to suppress grating lobes in the near-field. In order to verify the efficacy of these configurations, a hardware test platform was constructed. The platform permits largely automated evaluation of the near-field character of arbitrary array configurations. Using the test platform, several of the arrangements were constructed and evaluated. The results of these evaluations confirm that it is possible to reduce the grating lobes of sparse phased arrays in the near-field