DFT and BIST of a multichip module for high-energy physics experiments

Engineers at Politecnico di Torino designed a multichip module for high-energy physics experiments conducted on the Large Hadron Collider. An array of these MCMs handles multichannel data acquisition and signal processing. Testing the MCM from board to die level required a combination of DFT strategie

System, Circuit, And Method For Testing An Interconnect In A Multi-chip Substrate

A system for testing interconnects in multi-chip modules including a radio frequency resonator having a resonant circuit with a relatively high quality factor, the output of the resonant circuit being attached to a probe. Electrically coupled to the resonant circuit output is an apparatus to analyze the voltage signal output. The probe is applied to one end of an interconnect. When the probe is applied, the resonant frequency of the resonant circuit and the magnitude of the frequency response are altered due to the additional loading created by the interconnect. Due to the relatively high quality factor of the resonant circuit, the magnitude of the frequency response of the altered resonant circuit is measurably distinct from a predetermined reference magnitude at a predetermined reference frequency, thus indicating the existence of a defect. Additionally, the type of defect that exists is ascertainable by determining whether the resonant frequency of the altered resonant circuit is greater or less than the reference frequency by examining, for example, the phase response.Georgia Tech Research Corporatio

An Interconnection Architecture for Seamless Inter and Intra-Chip Communication Using Wireless Links

As semiconductor technologies continues to scale, more and more cores are being integrated on the same multicore chip. This increase in complexity poses the challenge of efficient data transfer between these cores. Several on-chip network architectures are proposed to improve the design flexibility and communication efficiency of such multicore chips. However, in a larger system consisting of several multicore chips across a board or in a System-in-Package (SiP), the performance is limited by the communication among and within these chips. Such systems, most commonly found within computing modules in typical data center nodes or server racks, are in dire need of an efficient interconnection architecture. Conventional interchip communication using wireline links involve routing the data from the internal cores to the peripheral I/O ports, travelling over the interchip channels to the destination chip, and finally getting routed from the I/O to the internal cores there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Furthermore, the intrachip and interchip communication architectures are separately designed to maximize design flexibility. Jointly designing them could, however, improve the communication efficiency significantly and yield better solutions. Previous attempts at this include an all-photonic approach that provides a unified inter/intra-chip optical network, based on recent progress in nano-photonic technologies. Works on wireless inter-chip interconnects successfully yielded better results than their wired counterparts, but their scopes were limited to establishing a single wireless connection between two chips rather than a communication architecture for a system as a whole. In this thesis, the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package is proposed. The design utilizes on-chip wireless transceivers with dimensions spanning up to tens of centimeters. It manages to seamlessly bind both intrachip and interchip communication architectures and enables direct chip-to-chip communication between the internal cores. It is shown through cycle accurate simulations that the proposed design increases the bandwidth and reduces the energy consumption when compared to the state-of-the-art wireline I/O based multichip communications

Thermosonic flip chip interconnection using electroplated copper column arrays

Published versio

Wafer-Level Parylene Packaging With Integrated RF Electronics for Wireless Retinal Prostheses

This paper presents an embedded chip integration technology that incorporates silicon housings and flexible Parylene-based microelectromechanical systems (MEMS) devices. Accelerated-lifetime soak testing is performed in saline at elevated temperatures to study the packaging performance of Parylene C thin films. Experimental results show that the silicon chip under test is well protected by Parylene, and the lifetime of Parylenecoated metal at body temperature (37°C) is more than 60 years, indicating that Parylene C is an excellent structural and packaging material for biomedical applications. To demonstrate the proposed packaging technology, a flexible MEMS radio-frequency (RF) coil has been integrated with an RF identification (RFID) circuit die. The coil has an inductance of 16 μH with two layers of metal completely encapsulated in Parylene C, which is microfabricated using a Parylene–metal–Parylene thin-film technology. The chip is a commercially available read-only RFID chip with a typical operating frequency of 125 kHz. The functionality of the embedded chip has been tested using an RFID reader module in both air and saline, demonstrating successful power and data transmission through the MEMS coil

Laser-assisted bumping for flip chip assembly

Published versio

Advanced information processing system for advanced launch system: Hardware technology survey and projections

The major goals of this effort are as follows: (1) to examine technology insertion options to optimize Advanced Information Processing System (AIPS) performance in the Advanced Launch System (ALS) environment; (2) to examine the AIPS concepts to ensure that valuable new technologies are not excluded from the AIPS/ALS implementations; (3) to examine advanced microprocessors applicable to AIPS/ALS, (4) to examine radiation hardening technologies applicable to AIPS/ALS; (5) to reach conclusions on AIPS hardware building blocks implementation technologies; and (6) reach conclusions on appropriate architectural improvements. The hardware building blocks are the Fault-Tolerant Processor, the Input/Output Sequencers (IOS), and the Intercomputer Interface Sequencers (ICIS)

Intelligent Reconfigurable Integrated Satellite Processor

We present our Intelligent Reconfigurable Integrated Satellite (IRIS) Processor. At the heart of the system are our reconfigurable vision chips which are capable of massively parallel analog processing. The smart vision chips are capable of not only centroiding and pattern recognition but also tracking and controlling devices including MEMs devices and active pixel arrays. In addition to discussing the active optic and active electronic devices, several small satellite system applications are presented along with experimental and simulation results

Bulk micromachining of silicon for MOEMS prototype

In this dissertation, the optical application of silicon micromachining technology was investigated in order to create the three-dimensional microstructures that can be used as the components for the MOEMS prototype. These microstructures were designed and fabricated by utilizing corner compensation techniques and silicon bulk micromachining technologies. The fabricated microstructures are silicon mirror arrays that have a 1250 μm etch depth and through-holes across the OE-MCM substrate that has sixteen-fan-out OCDN on front side and a 1mm thickness. Guided-wave OCDN on MCMs are designed and fabricated to meet the high-speed clocking requirements of next-generation digital systems through a realization of superior network bandwidth, low power consumption, and large fan-out capabilities. Two fabricated components were assembled to build the MOEMS prototype. From the fiber-to-waveguide butt coupler, the light signal is launched on the waveguide core, and the signal travels and splits along the waveguide. Then, the light signals reflect at the micromachined silicon mirrors which are located in the sixteen fan-out nodes. This device was characterized by measuring the excess loss at the sixteen fan-out nodes at the wavelengths of 1310 nm and 1550 nm. The results show low loss signal propagation and signal uniformity