1,582 research outputs found
Contribution to the design of continuous -time Sigma - Delta Modulators based on time delay elements
The research carried out in this thesis is focused in the development of a new class of data converters for digital radio. There are two main architectures for communication receivers which perform a digital demodulation. One of them is based on analog demodulation to the base band and digitization of the I/Q components. Another option is to digitize the band pass signal at the output of the IF stage using a bandpass Sigma-Delta modulator. Bandpass Sigma- Delta modulators can be implemented with discrete-time circuits, using switched capacitors or continuous-time circuits. The main innovation introduced in this work is the use of passive transmission lines in the loop filter of a bandpass continuous-time Sigma-Delta modulator instead of the conventional solution with gm-C or LC resonators. As long as transmission lines are used as replacement of a LC resonator in RF technology, it seems compelling that transmission lines could improve bandpass continuous-time Sigma-Delta modulators. The analysis of a Sigma- Delta modulator using distributed resonators has led to a completely new family of Sigma- Delta modulators which possess properties inherited both from continuous-time and discretetime Sigma-Delta modulators. In this thesis we present the basic theory and the practical design trade-offs of this new family of Sigma-Delta modulators. Three demonstration chips have been implemented to validate the theoretical developments. The first two are a proof of concept of the application of transmission lines to build lowpass and bandpass modulators. The third chip summarizes all the contributions of the thesis. It consists of a transmission line Sigma-Delta modulator which combines subsampling techniques, a mismatch insensitive circuitry and a quadrature architecture to implement the IF to digital stage of a receiver
A Highly Digital VCO-Based ADC With Lookup-Table-Based Background Calibration
CMOS technology scaling has enabled dramatic improvement for digital circuits both in terms of speed and power efficiency. However, most traditional analog-to-digital converter (ADC) architectures are challenged by ever-decreasing supply voltage. The improvement in time resolution enabled by increased digital speeds drives design towards time-domain architectures such as voltage-controlled-oscillator (VCO) based ADCs. The main challenge in VCO-based ADC design is mitigating the nonlinearity of VCO Voltage-to-frequency (V-to-f) characteristics. Achieving signal-to-noise ratio (SNR) performance better than 40dB requires some form of calibration, which can be realized by analog or digital techniques, or some combination. This dissertation proposes a highly digital, reconfigurable VCO-based ADC with lookup-table (LUT) based background calibration based on split ADC architecture. Each of the two split channels, ADC A and B , contains two VCOs in a differential configuration. This helps alleviate even-order distortions as well as increase the dynamic range. A digital controller on chip can reconfigure the ADCs\u27 sampling rates and resolutions to adapt to various application scenarios. Different types of input signals can be used to train the ADCâs LUT parameters through the simple, anti-aliasing continuous-time input to achieve target resolution. The chip is fabricated in a 180 nm CMOS process, and the active area of analog and digital circuits is 0.09 and 0.16mm^2, respectively. Power consumption of the core ADC function is 25 mW. Measured results for this prototype design with 12-b resolution show ENOB improves from uncorrected 5-b to 11.5-b with calibration time within 200 ms (780K conversions at 5 MSps sample rate)
Data acquisition techniques based on frequency-encoding applied to capacitive MEMS microphones
MenciĂłn Internacional en el tĂtulo de doctorThis thesis focuses on the development of capacitive sensor readout circuits
and data converters based on frequency-encoding. This research
has been motivated by the needs of consumer electronics industry, which
constantly demands more compact readout circuit for MEMS microphones
and other sensors. Nowadays, data acquisition is mainly based
on encoding signals in voltage or current domains, which is becoming
more challenging in modern deep submicron CMOS technologies.
Frequency-encoding is an emerging signal processing technique based
on encoding signals in the frequency domain. The key advantage of
this approach is that systems can be implemented using mostly-digital
circuitry, which benefits from CMOS technology scaling. Frequencyencoding
can be used to build phase referenced integrators, which can
replace classical integrators (such as switched-capacitor based integrators)
in the implementation of efficient analog-to-digital converters and
sensor interfaces. The core of the phase referenced integrators studied in
this thesis consists of the combination of different oscillator topologies
with counters and highly-digital circuitry.
This work addresses two related problems: the development of capacitive
MEMS sensor readout circuits based on frequency-encoding, and the
design and implementation of compact oscillator-based data converters
for audio applications.
In the first problem, the target is the integration of the MEMS sensor
into an oscillator circuit, making the oscillation frequency dependent on
the sensor capacitance. This way, the sound can be digitized by measuring
the oscillation frequency, using digital circuitry. However, a MEMS
microphone is a complex structure on which several parasitic effects can
influence the operation of the oscillator. This work presents a feasibility
analysis of the integration of a MEMS microphone into different oscillator
topologies. The conclusion of this study is that the parasitics of the
MEMS limit the performance of the microphone, making it inefficient.
In contrast, replacing conventional ADCs with frequency-encoding based
ADCs has proven a very efficient solution, which motivates the next
problem.
In the second problem, the focus is on the development of high-order
oscillator-based Sigma-Delta modulators. Firstly, the equivalence between classical
integrators and phase referenced integrators has been studied, followed
by an overview of state-of-art oscillator-based converters. Then,
a procedure to replace classical integrators by phase referenced integrators
is presented, including a design example of a second-order oscillator based
Sigma-Delta modulator. Subsequently, the main circuit impairments that
limit the performance of this kind of implementations, such as phase
noise, jitter or metastability, are described.
This thesis also presents a methodology to evaluate the impact of
phase noise and distortion in oscillator-based systems. The proposed
method is based on periodic steady-state analysis, which allows the rapid
estimation of the system dynamic range without resorting to transient
simulations. In addition, a novel technique to analyze the impact of
clock jitter in Sigma-Delta modulators is described.
Two integrated circuits have been implemented in 0.13 ÎŒm CMOS
technology to demonstrate the feasibility of high-order oscillator-based Sigma-Delta modulators. Both chips have been designed to feature secondorder
noise shaping using only oscillators and digital circuitry. The first
testchip shows a malfunction in the digital circuitry due to the complexity
of the multi-bit counters. The second chip, implemented using
single-bit counters for simplicity, shows second-order noise shaping and
reaches 103 dB-A of dynamic range in the audio bandwidth, occupying
only 0.04 mm2.Esta tesis se centra en el desarrollo de conversores de datos e interfaces
para sensores capacitivos basados en codificaciĂłn en frecuencia. Esta
investigaciĂłn estĂĄ motivada por las necesidades de la industria, que constantemente
demanda reducir el tamaño de este tipo de circuitos. Hoy en
dĂa, la adquisiciĂłn de datos estĂĄ basada principalmente en la codificaciĂłn
de señales en tensión o en corriente. Sin embargo, la implementación
de este tipo de soluciones en tecnologĂas CMOS nanomĂ©tricas presenta
varias dificultades.
La codificación de frecuencia es una técnica emergente en el procesado
de señales basada en codificar señales en el dominio de la frecuencia.
La principal ventaja de esta alternativa es que los sistemas pueden implementarse
usando circuitos mayoritariamente digitales, los cuales se
benefician de los avances de la tecnologĂa CMOS. La codificaciĂłn en
frecuencia puede emplearse para construir integradores referidos a la
fase, que pueden reemplazar a los integradores clĂĄsicos (como los basados
en capacidades conmutadas) en la implementaciĂłn de conversores
analĂłgico-digital e interfaces de sensores. Los integradores referidos a la
fase estudiados en esta tesis consisten en la combinaciĂłn de diferentes
topologĂas de osciladores con contadores y circuitos principalmente digitales.
Este trabajo aborda dos cuestiones relacionadas: el desarrollo de circuitos
de lectura para sensores MEMS capacitivos basados en codificaciĂłn
temporal, y el diseño e implementación de conversores de datos
compactos para aplicaciones de audio basados en osciladores.
En el primer caso, el objetivo es la integraciĂłn de un sensor MEMS
en un oscilador, haciendo que la frecuencia de oscilaciĂłn depe capacidad del sensor. De esta forma, el sonido puede ser digitalizado
midiendo la frecuencia de oscilaciĂłn, lo cual puede realizarse usando circuitos
en su mayor parte digitales. Sin embargo, un micrĂłfono MEMS es
una estructura compleja en la que mĂșltiples efectos parasĂticos pueden
alterar el correcto funcionamiento del oscilador. Este trabajo presenta
un anĂĄlisis de la viabilidad de integrar un micrĂłfono MEMS en diferentes
topologĂas de oscilador. La conclusiĂłn de este estudio es que los parasĂticos
del MEMS limitan el rendimiento del micrĂłfono, causando que esta
soluciĂłn no sea eficiente. En cambio, la implementaciĂłn de conversores
analĂłgico-digitales basados en codificaciĂłn en frecuencia ha demostrado
ser una alternativa muy eficiente, lo cual motiva el estudio del siguiente
problema.
La segunda cuestiĂłn estĂĄ centrada en el desarrollo de moduladores Sigma-Delta de alto orden basados en osciladores. En primer lugar se ha estudiado
la equivalencia entre los integradores clĂĄsicos y los integradores
referidos a la fase, seguido de una descripciĂłn de los conversores basados
en osciladores publicados en los Ășltimos años. A continuaciĂłn se
presenta un procedimiento para reemplazar integradores clĂĄsicos por integradores
referidos a la fase, incluyendo un ejemplo de diseño de un
modulador Sigma-Delta de segundo orden basado en osciladores. Posteriormente
se describen los principales problemas que limitan el rendimiento de este
tipo de sistemas, como el ruido de fase, el jitter o la metaestabilidad.
Esta tesis también presenta un nuevo método para evaluar el impacto
del ruido de fase y de la distorsiĂłn en sistemas basados en osciladores. El
método propuesto estå basado en simulaciones PSS, las cuales permiten
la rĂĄpida estimaciĂłn del rango dinĂĄmico del sistema sin necesidad de
recurrir a simulaciones temporales. AdemĂĄs, este trabajo describe una
nueva técnica para analizar el impacto del jitter de reloj en moduladores Sigma-Delta.
En esta tesis se han implementado dos circuitos integrados en tecnologĂa
CMOS de 0.13 ÎŒm, con el fin de demostrar la viabilidad de los
moduladores Sigma-Delta de alto orden basados en osciladores. Ambos chips han
sido diseñados para producir conformación espectral de ruido de segundo
orden, usando Ășnicamente osciladores y circuitos mayoritariamente digitales.
El primer chip ha mostrado un error en el funcionamiento de los
circuitos digitales debido a la complejidad de las estructuras multi-bit
utilizadas. El segundo chip, implementado usando contadores de un solo
bit con el fin de simplificar el sistema, consigue conformaciĂłn espectral
de ruido de segundo orden y alcanza 103 dB-A de rango dinĂĄmico en el
ancho de banda del audio, ocupando solo 0.04 mm2.Programa Oficial de Doctorado en IngenierĂa ElĂ©ctrica, ElectrĂłnica y AutomĂĄticaPresidente: Georges G.E. Gielen.- Secretario: JosĂ© Manuel de la Rosa.- Vocal: Ana Rus
Design of a low power switched-capacitor pipeline analog-to-digital converter
An Analog to Digital Converter (ADC) is a circuit which converts an analog signal into digital signal. Real world is analog, and the data processed by the computer or by other signal processing systems is digital. Therefore, the need for ADCs is obvious.
In this thesis, several novel designs used to improve ADCs operation speed and reduce ADC power consumption are proposed. First, a high speed switched source follower (SSF) sample and hold amplifier without feedthrough penalty is implemented and simulated. The SSF sample and hold amplifier can achieve 6 Bit resolution with sampling rate at 10Gs/s.
Second, a novel rail-to-rail time domain comparator used in successive approximation register ADC (SAR ADC) is implemented and simulated. The simulation results show that the proposed SAR ADC can only consume 1.3 muW with a 0.7 V power supply.
Finally, a prototype pipeline ADC is implemented and fabricated in an IBM 90nm CMOS process. The proposed design is validated using measurement on a fabricated silicon IC, and the proposed 10-bit ADC achieves a peak signal-to-noise- and-distortion-ratio (SNDR) of 47 dB. This SNDR translates to a figure of merit (FOM) of 2.6N/conversion-step with a 1.2 V power supply
Design of sigma-delta modulators for analog-to-digital conversion intensively using passive circuits
This thesis presents the analysis, design implementation and experimental evaluation of passiveactive discrete-time and continuous-time Sigma-Delta (ÎŁÎ) modulators (ÎŁÎMs) analog-todigital converters (ADCs).
Two prototype circuits were manufactured. The first one, a discrete-time 2nd-order ÎŁÎM, was designed in a 130 nm CMOS technology. This prototype confirmed the validity of the ultra incomplete settling (UIS) concept used for implementing the passive integrators. This circuit, clocked at 100 MHz and consuming 298 ÎŒW, achieves DR/SNR/SNDR of 78.2/73.9/72.8 dB, respectively, for a signal bandwidth of 300 kHz. This results in a Walden FoMW of 139.3 fJ/conv.-step and Schreier FoMS of 168 dB.
The final prototype circuit is a highly area and power efficient ÎŁÎM using a combination of a cascaded topology, a continuous-time RC loop filter and switched-capacitor feedback paths. The modulator requires only two low gain stages that are based on differential pairs. A systematic design methodology based on genetic algorithm, was used, which allowed decreasing the circuitâs sensitivity to the circuit componentsâ variations. This continuous-time, 2-1 MASH ÎŁÎM has been designed in a 65 nm CMOS technology and it occupies an area of just 0.027 mm2. Measurement results show that this modulator achieves a peak SNR/SNDR of 76/72.2 dB and DR of 77dB for an input signal bandwidth of 10 MHz, while dissipating 1.57 mW from a 1 V power supply voltage. The ÎŁÎM achieves a Walden FoMW of 23.6 fJ/level and a Schreier FoMS of 175 dB. The innovations proposed in this circuit result, both, in the reduction of the power consumption and of the chip size. To the best of the authorâs knowledge the circuit achieves the lowest Walden FOMW for ÎŁÎMs operating at signal bandwidth from 5 MHz to 50 MHz reported to date
Techniques for Frequency Synthesizer-Based Transmitters.
Internet of Things (IoT) devices are poised to be the largest market for the semiconductor industry. At the heart of a wireless IoT module is the radio and integral to any radio is the transmitter. Transmitters with low power consumption and small area are crucial to the ubiquity of IoT devices. The fairly simple modulation schemes used in IoT systems makes frequency synthesizer-based (also known as PLL-based) transmitters an ideal candidate for these devices. Because of the reduced number of analog blocks and the simple architecture, PLL-based transmitters lend themselves nicely to the highly integrated, low voltage nanometer digital CMOS processes of today. This thesis outlines techniques that not only reduce the power consumption and area, but also significantly improve the performance of PLL-based transmitters.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113385/1/mammad_1.pd
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