349 research outputs found

    Fast interconnect optimization

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    As the continuous trend of Very Large Scale Integration (VLSI) circuits technology scaling and frequency increases, delay optimization techniques for interconnect are increasingly important for achieving timing closure of high performance designs. For the gigahertz microprocessor and multi-million gate ASIC designs it is crucial to have fast algorithms in the design automation tools for many classical problems in the field to shorten time to market of the VLSI chip. This research presents algorithmic techniques and constructive models for two such problems: (1) Fast buffer insertion for delay optimization, (2) Wire sizing for delay optimization and variation minimization on non-tree networks. For the buffer insertion problem, this dissertation proposes several innovative speedup techniques for different problem formulations and the realistic requirement. For the basic buffer insertion problem, an O(n log2 n) optimal algorithm that runs much faster than the previous classical van GinnekenÂs O(n2) algorithm is proposed, where n is the number of buffer positions. For modern design libraries that contain hundreds of buffers, this research also proposes an optimal algorithm in O(bn2) time for b buffer types, a significant improvement over the previous O(b2n2) algorithm by Lillis, Cheng and Lin. For nets with small numbers of sinks and large numbers of buffer positions, a simple O(mn) optimal algorithm is proposed, where m is the number of sinks. For the buffer insertion with minimum cost problem, the problem is first proved to be NP-complete. Then several optimal and approximation techniques are proposed to further speed up the buffer insertion algorithm with resource control for big industrial designs. For the wire sizing problem, we propose a systematic method to size the wires of general non-tree RC networks. The new method can be used for delay optimization and variation reduction

    Covid-19 and its impacts on consumer decision-making process

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    The term "virus" derives from the Latin word for "venom" and refers to a microscopic infectious agent. On the other hand, "corona" is named by its shape to look like a crown ring – the scientists who coined the word coronavirus in 1968 reasoned that the virus they were studying under a microscope resembled a solar corona (Steinmetz, 2020). COVID-19 was introduced when it was first detected in late 2019 and used letters from CO-Rona-VI-rus D-isease (Bhargava, 2020). Corona infections were initially seen as cold in 1965 (Kahn & McIntosh, 2005), which is almost six decades ago. Corona was formerly thought to be a basic, non-fatal virus to human beings until 2002. Before the world witnessed a Severe Acute Respiratory Syndrome Coronavirus (SARS-CoV) outbreak in November 2002, it was assumed that this virus mainly infected animals. However, this was proven incorrect. Ten years after that, a new pathogenic coronavirus known as the Middle East Respiratory Syndrome Coronavirus (MERS-CoV) spread throughout the Middle East and caused a pandemic in several countries (Shereen et a., 2020)

    Interconnect tree optimization algorithm in nanometer very large scale integration designs

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    This thesis proposes a graph-based maze routing and buffer insertion algorithm for nanometer Very Large Scale Integration (VLSI) layout designs. The algorithm is called Hybrid Routing Tree and Buffer insertion with Look-Ahead (HRTB-LA). In recent VLSI designs, interconnect delay becomes a dominant factor compared to gate delay. The well-known technique to minimize the interconnect delay is by inserting buffers along the interconnect wires. In conventional buffer insertion algorithms, the buffers are inserted on the fixed routing paths. However, in a modern design, there are macro blocks that prohibit any buffer insertion in their respective area. Most of the conventional buffer insertion algorithms do not consider these obstacles. In the presence of buffer obstacles, post routing algorithm may produce poor solution. On the other hand, simultaneous routing and buffer insertion algorithm offers a better solution, but it was proven to be NP-complete. Besides timing performance, power dissipation of the inserted buffers is another metric that needs to be optimized. Research has shown that power dissipation overhead due to buffer insertions is significantly high. In other words, interconnect delay and power dissipation move in opposite directions. Although many methodologies to optimize timing performance with power constraint have been proposed, no algorithm is based on grid graph technique. Hence, the main contribution of this thesis is an efficient algorithm using a hybrid approach for multi-constraint optimization in multi-terminal nets. The algorithm uses dynamic programming to compute the interconnect delay and power dissipation of the inserted buffers incrementally, while an effective runtime is achieved with the aid of novel look-ahead and graph pruning schemes. Experimental results prove that HRTB-LA is able to handle multi-constraint optimizations and produces up to 47% better solution compared to a post routing buffer insertion algorithm in comparable runtime

    Mechanism and kinetics of homogeneous catalysis

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    A model-based approach using a diverse set of data including monomer consumption, evolution of molecular weight, and end-group analysis was employed to determine each of the reaction specific rate constants involved in 1-hexene polymerization process catalyzed by a family of group IV single-site catalysts. The primary set of elementary reaction steps included initiation, normal propagation, misinsertion, recovery from misinsertion, monomer independent and dependent chain transfer. Robust determination of kinetic constants and reaction mechanisms for a series of Group IV amine bis-phenolate complexes led to the development of several structure−activity relationships.^ For some of the catalysts of the bis-phenolate family the primary set of elementary reactions had proven inadequate and further investigation using the analysis developed here revealed the presence of additional key reaction steps. The kinetic study of the Zr[tBu-ONTHFO]Bn2/B(C 6F5)3 system under sub-stoichiometric activator conditions uncovered the formation of the binuclear complex (BNC) consisting of the neutral catalytic species and an active site connected via degenerative transfer of benzyl ligand. The kinetic study of the Zr[tBu-ONNEt2O]Bn2/B(C6F5)3 system showed that a special polymeric site was formed which was capable to incorporate the growing oligomer chains attached to the normal active site to form branched polymer.^ The approach was next applied to studying the kinetics of other catalytic systems, e.g., the zwitterionic ring-opening polymerization using N-heterocyclic carbene, where several new reaction steps were proposed and then experimentally validated, including the attack of active zwitterions on cyclic chains that leads to high molecular weight cyclic poly(caprolactones)

    Fast algorithms for slew constrained minimum cost buffering

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    Fast Algorithms for Slew-Constrained Minimum Cost Buffering

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