Network-on-Chip Synchronization

Technology scaling has enabled the number of cores within a System on Chip (SoC) to increase significantly. Globally Asynchronous Locally Synchronous (GALS) systems using Dynamic Voltage and Frequency Scaling (DVFS) operate each of these cores on distinct and dynamic clock domains. The main communication method between these cores is increasingly more likely to be a Network-on-Chip (NoC). Typically, the interfaces between these clock domains experience multi-cycle synchronization latencies due to their use of “brute-force” synchronizers. This dissertation aims to improve the performance of NoCs and thereby SoCs as a whole by reducing this synchronization latency. First, a survey of NoC improvement techniques is presented. One such improvement technique: a multi-layer NoC, has been successfully simulated. Given how one of the most commonly used techniques is DVFS, a thorough analysis and simulation of brute-force synchronizer circuits in both current and future process technologies is presented. Unfortunately, a multi-cycle latency is unavoidable when using brute-force synchronizers, so predictive synchronizers which require only a single cycle of latency have been proposed. To demonstrate the impact of these predictive synchronizer circuits at a high level, multi-core system simulations incorporating these circuits have been completed. Multiple forms of GALS NoC configurations have been simulated, including multi-synchronous, NoC-synchronous, and single-synchronizer. Speedup on the SPLASH benchmark suite was measured to directly quantify the performance benefit of predictive synchronizers in a full system. Additionally, Mean Time Between Failures (MTBF) has been calculated for each NoC synchronizer configuration to determine the reliability benefit possible when using predictive synchronizers

CDC logic verification in RTL design

Abstract. This bachelor’s thesis provides overview of the clock domain crossing verification in RTL design. Metastability problem and different synchronization methods are explained, and the CDC verification flow is introduced. The work is focused to discuss about different challenges in the CDC verification.CDC Logic Verification in RTL Design CDC logiikan tarkastaminen RTL suunnittellussa. Tiivistelmä. Tämä kandidaatintyö antaa yleiskatsauksen kelloalueylitysten verifiointiin RTL suunnittelussa. Metastabiilisuus ja erilaiset synkronointitavat selitetään sekä CDC verifiointiprosessi esitetään. Työ painottuu tarkastelemaan erilaisia haasteita CDC verifioinnissa

Design of variation-tolerant synchronizers for multiple clock and voltage domains

PhD ThesisParametric variability increasingly affects the performance of electronic circuits as the fabrication technology has reached the level of 32nm and beyond. These parameters may include transistor Process parameters (such as threshold voltage), supply Voltage and Temperature (PVT), all of which could have a significant impact on the speed and power consumption of the circuit, particularly if the variations exceed the design margins. As systems are designed with more asynchronous protocols, there is a need for highly robust synchronizers and arbiters. These components are often used as interfaces between communication links of different timing domains as well as sampling devices for asynchronous inputs coming from external components. These applications have created a need for new robust designs of synchronizers and arbiters that can tolerate process, voltage and temperature variations. The aim of this study was to investigate how synchronizers and arbiters should be designed to tolerate parametric variations. All investigations focused mainly on circuit-level and transistor level designs and were modeled and simulated in the UMC90nm CMOS technology process. Analog simulations were used to measure timing parameters and power consumption along with a “Monte Carlo” statistical analysis to account for process variations. Two main components of synchronizers and arbiters were primarily investigated: flip-flop and mutual-exclusion element (MUTEX). Both components can violate the input timing conditions, setup and hold window times, which could cause metastability inside their bistable elements and possibly end in failures. The mean-time between failures is an important reliability feature of any synchronizer delay through the synchronizer. The MUTEX study focused on the classical circuit, in addition to a number of tolerance, based on increasing internal gain by adding current sources, reducing the capacitive loading, boosting the transconductance of the latch, compensating the existing Miller capacitance, and adding asymmetry to maneuver the metastable point. The results showed that some circuits had little or almost no improvements, while five techniques showed significant improvements by reducing τ and maintaining high tolerance. Three design approaches are proposed to provide variation-tolerant synchronizers. wagging synchronizer proposed to First, the is significantly increase reliability over that of the conventional two flip-flop synchronizer. The robustness of the wagging technique can be enhanced by using robust τ latches or adding one more cycle of synchronization. The second approach is the Metastability Auto-Detection and Correction (MADAC) latch which relies on swiftly detecting a metastable event and correcting it by enforcing the previously stored logic value. This technique significantly reduces the resolution time down from uncertain synchronization technique is proposed to transfer signals between Multiple- Voltage Multiple-Clock Domains (MVD/MCD) that do not require conventional level-shifters between the domains or multiple power supplies within each domain. This interface circuit uses a synchronous set and feedback reset protocol which provides level-shifting and synchronization of all signals between the domains, from a wide range of voltage-supplies and clock frequencies. Overall, synchronizer circuits can tolerate variations to a greater extent by employing the wagging technique or using a MADAC latch, while MUTEX tolerance can suffice with small circuit modifications. Communication between MVD/MCD can be achieved by an asynchronous handshake without a need for adding level-shifters.The Saudi Arabian Embassy in London, Umm Al-Qura University, Saudi Arabi

Deterministic and random phase synchronizers

This work study two groups of synchronizers, namely the Deterministic Phase Synchronizer and the Random Phase Synchronizer. The difference between them is only inside of the phase comparator. In the first group, the VCO (Voltage Controlled Oscillator) synchronizes with the input deterministic phase of an expected periodic transition. In the second group the VCO synchronizes with the input random phase of an unexpected no periodic transition. Each group is studied under four topologies (analog, hybrid, combinational and sequential). The objective is to evaluate the two synchronizers groups with the four topologies and to observe their jitter behaviors with the noise

Prefilter bandwidth effects in sequential symbol synchronizers based on clock sampling by positive transitions

This work studies the effects of the prefilter bandwidth in the sequential symbol synchronizers based on clock sampling by positive transitions. The prefilter bandwidth B is switched between three values, namely B1=∞, B2=2. tx and B3=1. tx, where tx is the bit rate. The synchronizer has two variants, one discrete and other continuous. Each variant has two versions, one manual and other automatic. The objective is to study the prefilter bandwidth with the four synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio)

Prefilter bandwidth effects in data symbol phase synchronizers of open loop

This work studies the effects of the prefilter bandwidth on the open loop symbol synchronizers. We consider three different prefilter bandwidth, namely, B1=¥ ( infinite), B2=2.tx and B3=1.tx, where tx is the transmission rate. We consider also four open loop symbol synchronizers, namely, the tank (tank), the SAW (SAW), the monostable (mon), and the astable (ast). The objective is to study the prefilter bandwidth with the four open loop symbol synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio)

Sequential symbol synchronizers based on clock sampling by positive transitions

This work presents a sequential symbol synchronizer, that was discovered by us, and its functioning principle is based on the clock sampling by the input positive data transitions. This synchronizer has two topologies, namely the discrete and the continuous. Also, each topology has two versions which are the manual and the automatic. These synchronizers are very interesting, because the previous adjust of the manual version isn’t critical. The objective is to study the four synchronizers and to evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal to Noise Ratio)

Sequential symbol synchronizers based on pulse comparison operating by positive transitions at quarter rate

This work presents the sequential symbol synchronizer based on pulse comparison by positive transitions at quarter rate (txp/4). Their performance is compared with a reference synchronizer by both transitions at the rate (tx). For the reference and proposed synchronizer we consider two versions which are the manual (m) and the automatic (a). The objective is to study the four synchronizers and evaluate their output jitter UIRMS (Unit Interval Root Mean Square) versus input SNR (Signal Noise Ratio)