Wireless power and network synchronisation for agricultural and industrial remote sensors using low voltage CMOS Harvesting and Data Demodulator IC

This paper presents a wide area medium frequency loosely coupled magnetic energy harvesting system with power delivery and network synchronisation for remote sensors, intended for agricultural and industrial environments. Intended for situations with poor service access, power is supplied from a source via a large area loop. Receiver nodes may use ferrite cored coils for good efficiency with modest volume. Transmission of low bandwidth network synchronisation data permits very low operational duty cycle with the need for real time clocks or wake up receivers and their associated power drain. As a key enabler for the system, a full custom energy harvester and QPSK data demodulator IC has been designed and fabricated in a commercial 180nm CMOS technology. The IC occupies 0.54mm2 and can deliver 10.3µW at 3V to an external battery or capacitor. With standard MOS device thresholds the rectifier can start from cold with only 250mV peak from the antenna loop, and the battery charge output is delivered with 330mV peak input. Results are presented from laboratory evaluation and from preliminary measurements in the field with a 10m x 10m loop driven at 800kHz

Diseño e implementación de un demodulador QPSK utilizando una técnica de tendencia central

En este trabajo se describe la forma de aplicar la mediana para la demodulación de una señal QPSK y de esa manera recuperar los bits de datos. Los resultados obtenidos muestran que la mediana es una técnica adecuada debido a su simplicidad. Para la modulación de las señales se usaron dos técnicas: síntesis digital directa (DDS) y almacenamiento de fases en memoria. Se compararon estas técnicas para probar posteriormente el funcionamiento del demodulador QPSK. Dicha comparación consistió en probar su eficiencia usando parámetros tales como: consumo de potencia y cantidad de elementos usados; se concluyó que la técnica de memorias es la óptima. Los moduladores y el demodulador con la técnica de tendencia central se diseñaron en lenguaje VHDL y se implementaron en una tarjeta FPGA Virtex-5 de Xilinx

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Low Power Circuit Design in Sustainable Self Powered Systems for IoT Applications

The Internet-of-Things (IoT) network is being vigorously pushed forward from many fronts in diverse research communities. Many problems are still there to be solved, and challenges are found among its many levels of abstraction. In this thesis we give an overview of recent developments in circuit design for ultra-low power transceivers and energy harvesting management units for the IoT. The first part of the dissertation conducts a study of energy harvesting interfaces and optimizing power extraction, followed by power management for energy storage and supply regulation. we give an overview of the recent developments in circuit design for ultra-low power management units, focusing mainly in the architectures and techniques required for energy harvesting from multiple heterogeneous sources. Three projects are presented in this area to reach a solution that provides reliable continuous operation for IoT sensor nodes in the presence of one or more natural energy sources to harvest from. The second part focuses on wireless transmission, To reduce the power consumption and boost the Tx energy efficiency, a novel delay cell exploiting current reuse is used in a ring-oscillator employed as the local oscillator generator scheme. In combination with an edge-combiner power amplifier, the Tx showed a measured energy efficiency of 0.2 nJ=bit and a normalized energy efficiency of 3.1 nJ=bit:mW when operating at output power levels up to -10 dBm and data rates of 3 Mbps

Recent Trends in Communication Networks

In recent years there has been many developments in communication technology. This has greatly enhanced the computing power of small handheld resource-constrained mobile devices. Different generations of communication technology have evolved. This had led to new research for communication of large volumes of data in different transmission media and the design of different communication protocols. Another direction of research concerns the secure and error-free communication between the sender and receiver despite the risk of the presence of an eavesdropper. For the communication requirement of a huge amount of multimedia streaming data, a lot of research has been carried out in the design of proper overlay networks. The book addresses new research techniques that have evolved to handle these challenges

Design of Low-Power Short-Distance Transceiver for Wireless Sensor Networks

Ph.DDOCTOR OF PHILOSOPH

Recent Advances in Wireless Communications and Networks

This book focuses on the current hottest issues from the lowest layers to the upper layers of wireless communication networks and provides "real-time" research progress on these issues. The authors have made every effort to systematically organize the information on these topics to make it easily accessible to readers of any level. This book also maintains the balance between current research results and their theoretical support. In this book, a variety of novel techniques in wireless communications and networks are investigated. The authors attempt to present these topics in detail. Insightful and reader-friendly descriptions are presented to nourish readers of any level, from practicing and knowledgeable communication engineers to beginning or professional researchers. All interested readers can easily find noteworthy materials in much greater detail than in previous publications and in the references cited in these chapters

An MF energy harvesting receiver with slow QPSK control data demodulator for wide area low duty cycle applications

A receiver circuit is presented for use providing power and control for widely deployed sensor nodes, where the source of the power and control data are delivered by a very loosely-coupled medium frequency (MF) magnetic link. The receiver consists of a low start-up voltage rectifier, an inductor-capacitor (LC) antenna tuning circuit, an ultra-low power phase shift-keying (PSK) data demodulator, together with a power management unit (PMU). In such an application, accurately tuned high quality factor (Q) receiving coils are essential to maximise the received voltage, and hence the operating range for reliable startup. Slow QPSK data modulation is used for control and the timing needed for very low duty cycle networks. The receiver circuit occupies 0.89mm2 in a 0.18μm CMOS process with N and P thresholds of 0.355V and-0.405V respectively. The rectifier can start reliably with an input 220mV below the MOS thresholds (Vth). With an equivalent load of 100k Ω, the rectifier power conversion efficiency (PCE) peaks at 42 % and the dynamic reconfiguration maintains this above 25% up to 700mV input. The sub-sampling demodulator architecture is specifically designed to deal with the slow phase changes in the received signal resulting from the narrow receive bandwidth. The demodulator consumes 3.62μA from an internal 0.63V supply, achieving 10-6 bit-error-rate (BER) at 15.5kbps with a 1MHz carrier and an antenna Q of 10, while consuming 2.28μW.</p

International program for Earth observations

During the 1990 summer session of the International Space University, graduate students of many different countries and with various academic backgrounds carried out a design project that focused on how to meet the most pressing environmental information requirements of the 1990's. The International Program for Earth Observations (IPEO) is the result of the students labor. The IPEO report examines the legal and institutional, scientific, engineering and systems, financial and economic, and market development approaches needed to improve international earth observations and information systems to deal with environmental issues of global importance. The IPEO scenario is based on the production of a group of lightweight satellites to be used in global remote sensing programs. The design and function of the satellite is described in detail