MIMO Transmission with Residual Transmit-RF Impairments

Physical transceiver implementations for multiple-input multiple-output (MIMO) wireless communication systems suffer from transmit-RF (Tx-RF) impairments. In this paper, we study the effect on channel capacity and error-rate performance of residual Tx-RF impairments that defy proper compensation. In particular, we demonstrate that such residual distortions severely degrade the performance of (near-)optimum MIMO detection algorithms. To mitigate this performance loss, we propose an efficient algorithm, which is based on an i.i.d. Gaussian model for the distortion caused by these impairments. In order to validate this model, we provide measurement results based on a 4-stream Tx-RF chain implementation for MIMO orthogonal frequency-division multiplexing (OFDM).Comment: to be presented at the International ITG Workshop on Smart Antennas - WSA 201

VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems

The rapid evolution of wireless access is creating an ever changing variety of standards for indoor and outdoor environments. The real-time processing demands of wireless data rates in excess of 100 Mbps is a challenging problem for architecture design and verification. In this paper, we consider current trends in VLSI architecture and in rapid prototyping testbeds to evaluate these systems. The key phases in multi-standard system design and prototyping include: Algorithm Mapping to Parallel Architectures – based on the real-time data and sampling rate and the resulting area, time and power complexity; Configurable Mappings and Design Exploration – based on heterogeneous architectures consisting of DSP, programmable application-specific instruction (ASIP) processors, and co-processors; and Verification and Testbed Integration – based on prototype implementation on programmable devices and integration with RF units.Nokia Foundation FellowshipNokia CorporationNational InstrumentsNational Science Foundatio

大規模システムLSI設計のための統一的ハードウェア・ソフトウェア協調検証手法

Currently, the complexity of embedded LSI system is growing faster than the productivity of system design. This trend results in a design productivity gap, particularly in tight development time. Since the verification task takes bigger part of development task, it becomes a major challenge in LSI system design. In order to guarantee system reliability and quality of results (QoR), verifying large coverage of system functionality requires huge amount of relevant test cases and various scenario of evaluations. To overcome these problems, verification methodology is evolving toward supporting higher level of design abstraction by employing HW-SW co-verification. In this study, we present a novel approach for verification LSI circuit which is called as unified HW/SW co-verification framework. The study aims to improve design efficiency while maintains implementation consistency in the point of view of system-level performance. The proposed data-driven simulation and flexible interface of HW and SW design become the backbone of verification framework. In order to avoid time consuming, prone error, and iterative design spin-off in a large team, the proposed framework has to support multiple design abstractions. Hence, it can close the loop of design, exploration, optimization, and testing. Furthermore, the proposed methodology is also able to co-operate with system-level simulation in high-level abstraction, which is easy to extend for various applications and enables fast-turn around design modification. These contributions are discussed in chapter 3. In order to show the effectiveness and the use-cases of the proposed verification framework, the evaluation and metrics assessments of Very High Throughput wireless LAN system design are carried out. Two application examples are provided. The first case in chapter 4 is intended for fast verification and design exploration of large circuit. The Maximum Likelihood Detection (MLD) MIMO decoder is considered as Design Under Test (DUT). The second case, as presented in chapter 5, is the evaluation for system-level simulation. The full transceiver system based on IEEE 802.11ac standard is employed as DUT. Experimental results show that the proposed verification approach gives significant improvements of verification time (e.g. up to 10,000 times) over the conventional scheme. The proposed framework is also able to support various schemes of system level evaluations and cross-layer evaluation of wireless system.九州工業大学博士学位論文 学位記番号：情工博甲第328号 学位授与年月日：平成29年6月30日1 Introduction|2 Design and Verification in LSI System Design|3 Unified HW/SW Co-verification Methodology|4 Fast Co-verification and Design Exploration in Complex Circuits|5 Unified System Level Simulator for Very High Throughput Wireless Systems|6 Conclusion and Future Work九州工業大学平成29年

High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm

In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage of the trellis maps to a possible complex-valued symbol transmitted by antenna. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4x4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology.With a 1.18 mm2 core area, the folded detector can achieve a throughput of 2.1 Gbps.With a 3.19 mm2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps

Development of Wireless Techniques in Data and Power Transmission - Application for Particle Physics Detectors

Wireless techniques have developed extremely fast over the last decade and using them for data and power transmission in particle physics detectors is not science- fiction any more. During the last years several research groups have independently thought of making it a reality. Wireless techniques became a mature field for research and new developments might have impact on future particle physics experiments. The Instrumentation Frontier was set up as a part of the SnowMass 2013 Community Summer Study [1] to examine the instrumentation R&D for the particle physics research over the coming decades: {\guillemotleft} To succeed we need to make technical and scientific innovation a priority in the field {\guillemotright}. Wireless data transmission was identified as one of the innovations that could revolutionize the transmission of data out of the detector. Power delivery was another challenge mentioned in the same report. We propose a collaboration to identify the specific needs of different projects that might benefit from wireless techniques. The objective is to provide a common platform for research and development in order to optimize effectiveness and cost, with the aim of designing and testing wireless demonstrators for large instrumentation systems

A low-complexity linear and iterative receiver architecture for multi-antenna communication systems

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2004.Vita.Includes bibliographical references (leaves 60-62).Multi-antenna systems have been shown to significantly improve channel capacity in wireless environments. The focus of this thesis is on the design of low-complexity multi-antenna receiver architectures for communication networks and their demonstration in a real-time wireless environment. Our practical realization of an orthogonal frequency-division multi-antenna receiver is capable of several forms of linear and iterative detection. Our implementation is based on a division-free reformulation of standard minimum mean-squared-error detection algorithms and uses complex dot-products as the basic building blocks of a folded-pipelined architecture. This folded-pipelined architecture provides significant area savings over non-folded approaches. The demonstration of our receiver architecture is carried out on a rapid-prototyping FPGA communication system. This prototype is used to validate our design and complement theoretical and simulated results with real-time laboratory measurements in a typical office environment.by David Louis Milliner.M.Eng