UVM Verification of an SPI Master Core

In today’s world, more and more functionalities in the form of IP cores are integrated into a single chip or SOC. System-level verification of such large SOCs has become complex. The modern trend is to provide pre-designed IP cores with companion Verification IP. These Verification IPs are independent, scalable, and reusable verification components. The SystemVerilog language is based on object-oriented principles and is the most promising language to develop a complete verification environment with functional coverage, constrained random testing and assertions. The Universal Verification Methodology, written in SystemVerilog, is a base class library of reusable verification components. This paper discusses a Universal Verification Methodology based environment for testing a Wishbone compliant SPI master controller core. A multi-layer testbench was developed which consists of a Wishbone bus functional model, SPI slave model, driver, scoreboard, coverage analysis, and assertions developed using various properties of SystemVerilog an the UVM library. Later, constrained random testing using vectors driven into the DUT for higher functional coverage is discussed. The verification results shows the effectiveness and feasibility of the proposed verification environment

OVM compliant verification for a wishbone compatible i2c master controller core

Increasing design complexity and concurrency of Integrated Circuits has made traditional directed testbenches an unworkable solution for testing. Today, testing as a word has been substituted with verification. Verification engineers have to ensure what goes to the factory for manufacturing is an accurate representation of the design specification. Inter Integrated Circuit (I2C) bus is a very widely used communication protocol in embedded system design due to its hardware simplicity and high data transfer rates capability. Most ICs incorporate I2C interface. Thus the ASIC design process of these ICs calls for robust, independent and exhaustive verification to reduce the risks of their failures. Open Verification Methodology (OVM) is an open source verification methodology library intended to run on multiple platforms and be supported by multiple EDA vendors. This thesis attempts to study and hence introduces a comprehensive verification environment for the latest specifications of the I2C bus protocol realized in the OVM platform, a new industry standard for comprehensive verification due to its rich base classes and OOP features. This work has been challenging since very few work has been reported in this domain for reference

XPA: An Open Source IDE for XACML Policies

This paper presents XPA (XACML Policy Analyzer), an open source IDE (Integrated Development Environment) for testing, debugging, and mutating XACML 3.0 policies. XACML is an OASIS standard for specifying attributebased access control policies. XPA provides a variety of new techniques for generating test cases from policies, localizing bugs in faulty policies, and repairing faulty policy elements. XPA has been applied to numerous XACML policies from the literature and real-world applications. These policies have been used to quantitatively evaluate the effectiveness of various testing and debugging methods. For system developers and administrators, XPA is a practical IDE for developing dependable XACML policies. For access control researchers, XPA offers a versatile toolkit for studying and evaluating new testing, debugging, and verification techniques

Space Suit Portable Life Support System (PLSS) 2.0 Unmanned Vacuum Environment Testing

For the first time in more than 30 years, an advanced space suit Portable Life Support System (PLSS) design was operated inside a vacuum chamber representative of the flight operating environment. The test article, PLSS 2.0, was the second system-level integrated prototype of the advanced PLSS design, following the PLSS 1.0 Breadboard that was developed and tested throughout 2011. Whereas PLSS 1.0 included five technology development components with the balance the system simulated using commercial-off-the-shelf items, PLSS 2.0 featured first generation or later prototypes for all components less instrumentation, tubing and fittings. Developed throughout 2012, PLSS 2.0 was the first attempt to package the system into a flight-like representative volume. PLSS 2.0 testing included an extensive functional evaluation known as Pre-Installation Acceptance (PIA) testing, Human-in-the-Loop testing in which the PLSS 2.0 prototype was integrated via umbilicals to a manned prototype space suit for 19 two-hour simulated EVAs, and unmanned vacuum environment testing. Unmanned vacuum environment testing took place from 1/9/15-7/9/15 with PLSS 2.0 located inside a vacuum chamber. Test sequences included performance mapping of several components, carbon dioxide removal evaluations at simulated intravehicular activity (IVA) conditions, a regulator pressure schedule assessment, and culminated with 25 simulated extravehicular activities (EVAs). During the unmanned vacuum environment test series, PLSS 2.0 accumulated 378 hours of integrated testing including 291 hours of operation in a vacuum environment and 199 hours of simulated EVA time. The PLSS prototype performed nominally throughout the test series, with two notable exceptions including a pump failure and a Spacesuit Water Membrane Evaporator (SWME) leak, for which post-test failure investigations were performed. In addition to generating an extensive database of PLSS 2.0 performance data, achievements included requirements and operational concepts verification, as well as demonstration of vehicular interfaces, consumables sizing and recharge, and water quality control

The Hyper-X Flight Systems Validation Program

For the Hyper-X/X-43A program, the development of a comprehensive validation test plan played an integral part in the success of the mission. The goal was to demonstrate hypersonic propulsion technologies by flight testing an airframe-integrated scramjet engine. Preparation for flight involved both verification and validation testing. By definition, verification is the process of assuring that the product meets design requirements; whereas validation is the process of assuring that the design meets mission requirements for the intended environment. This report presents an overview of the program with emphasis on the validation efforts. It includes topics such as hardware-in-the-loop, failure modes and effects, aircraft-in-the-loop, plugs-out, power characterization, antenna pattern, integration, combined systems, captive carry, and flight testing. Where applicable, test results are also discussed. The report provides a brief description of the flight systems onboard the X-43A research vehicle and an introduction to the ground support equipment required to execute the validation plan. The intent is to provide validation concepts that are applicable to current, follow-on, and next generation vehicles that share the hybrid spacecraft and aircraft characteristics of the Hyper-X vehicle

Functional Verification Test Time Reduction Through Behavioral Functional Model

Design verification is an essential step in every design development process for quality assurance. However, the verification portion is the bottleneck in most of design development which takes up 60% of the overall design development period. As the complexity of the design increases, it increases the verification lead time which will then lead to potential failure of the design to meet market on time. One of the key factor in slowing down the design verification flow is the long simulation time during the pre-silicon functional testing. The long test simulation time issue is seen in NAND Intellectual Property (IP) pre-silicon validation. Therefore in this project, a behavioral Bus Functional Model (BFM) is implemented for NAND IP to improve the test simulation time. The BFM has been successfully implemented to validate NAND IP. Simulation of test with similar functional testing scenarios have been exercised on NAND IP in existing verification environment and in verification environment with BFM integrated. As a result, the BFM is found to have behaved accurately comparing with the existing functional Register Transfer Level (RTL) to validate NAND IP. Comparison has also shown the test simulation time through the environment with BFM integrated using Verilog Compiler Simulator (VCS) had shown significant average improvement of 92.8%. Therefore the implemented BFM is justified to be a suitable use on NAND IP validation

Real-Time Hardware-in-the-Loop Simulation of Ares I Launch Vehicle

The Ares Real-Time Environment for Modeling, Integration, and Simulation (ARTEMIS) has been developed for use by the Ares I launch vehicle System Integration Laboratory at the Marshall Space Flight Center. The primary purpose of the Ares System Integration Laboratory is to test the vehicle avionics hardware and software in a hardware - in-the-loop environment to certify that the integrated system is prepared for flight. ARTEMIS has been designed to be the real-time simulation backbone to stimulate all required Ares components for verification testing. ARTE_VIIS provides high -fidelity dynamics, actuator, and sensor models to simulate an accurate flight trajectory in order to ensure realistic test conditions. ARTEMIS has been designed to take advantage of the advances in underlying computational power now available to support hardware-in-the-loop testing to achieve real-time simulation with unprecedented model fidelity. A modular realtime design relying on a fully distributed computing architecture has been implemented

Simulation and Integrated Testing of Process Models of PFBR Operator Training Simulator

AbstractHigh fidelity Full Scope Operator Training Simulators play a key role in imparting plant related knowledge to the operating personnel in an effective way. It provides a platform for training the operators on normal and emergency conditions including all types of scenarios that would arise in any Nuclear Power Plant. The scenario based training helps the plant operator to handle a crisis in an efficient manner with the ultimate goal of safe and efficient operation of the plant.This paper discusses about the general description of PFBR Operator Training Simulator, modeling and simulation of various process models, the complexities involved etc. It also covers the associated process logics, controls, display of alarms and indications, malfunctions and transient incidents related to each process model, integration with other sub systems, individual process model testing, integrated performance testing and verification and validation of models. Simulation of process models are broadly classified into two main categories namely, External Models - that are developed in-house and ported to the simulator environment and Internal Models - that are developed using Simulation Tool. External Models are tested on the desk top for intended functioning and after obtaining satisfactory results, the models are ported to the simulator base wherein the Logical and Virtual Panel Models are built to represent a real system of the plant. Internal Models are built using the Simulation Tools and integrated with the External Models after testing. Combination of External and Internal Model represents the total plant and the performance testing is conducted in an Integrated Mode to qua lify the Process Models for training purpose