A Review on Multilevel Inverter Topologies

In this paper, a brief review of the multilevel inverter (MLI) topologies is presented. The two-level Voltage Source Inverter (VSI) requires a suitable filter to produce sinusoidal output waveforms. The high-frequency switching and the PWM method are used to create output waveforms with the least amount of ripples. Due to the switching losses, the traditional two-level inverter has some restrictions when running at high frequencies. For addressing this problem, multilevel inverters (MLI) with lower switching frequencies and reduced total harmonic distortion (THD) are employed, eliminating the requirement for filters and bulky transformers. Furthermore, improved performance at the high switching frequency, higher power quality (near to pure sinusoidal), and fewer switching losses are just a few of the benefits of MLI inverters. However, each switch has to have its own gate driver for implementing MLI, which adds to the system's complexity. Therefore, reducing the number of switches of MLI is necessary. This paper presents a review of some of the different current topologies using a lower number of switches. Doi: 10.28991/ESJ-2022-06-01-014 Full Text: PD

Cascaded Converters For Integration And Management Of Grid Level Energy Storage Systems

ABSTRACT CASCADED CONVERTERS FOR INTEGRATION AND MANAGEMENT OF GRID-LEVEL ENERGY STORAGE SYSTEMS by ZUHAIR ALAAS December 2017 Advisor: Dr. Caisheng Wang Major: ELECTRICAL ENGINEERING Degree: Doctor of Philosophy This research work proposes two cascaded multilevel inverter structures for BESS. The gating and switching control of switching devices in both inverter typologies are done by using a phase-shifted PWM scheme. The first proposed isolated multilevel inverter is made up of three-phase six-switch inverter blocks with a reduced number of power components compared with traditional isolated CHB. The suggested isolated converter has only one battery string for three-phase system that can be used for high voltage and high power applications such as grid connected BESS and alternative energy systems. The isolated inverter enables dq frame based simple control and eliminates the issues of single-phase pulsating power, which can cause detrimental impacts on certain dc sources. Simulation studies have been carried out to compare the proposed isolated multi-level inverter with an H-bridge cascaded transformer inverter. The simulation results verified the performance of the isolated inverter. The second proposed topology is a Hierarchal Cascaded Multilevel Converter (HCMC) with phase to phase SOC balancing capability which also for high voltage and high power battery energy storage systems. The HCMC has a hybrid structure of half-bridge converters and H-bridge inverters and the voltage can be hierarchically cascaded to reach the desired value at the half-bridge and the H-bridge levels. The uniform SOC battery management is achieved by controlling the half-bridge converters that are connected to individual battery modules/cells. Simulation studies and experimental results have been carried on a large scale battery system under different operating conditions to verify the effectiveness of the proposed inverters. Moreover, this dissertation presents a new three-phase SOC equalizing circuit, called six-switch energy-level balancing circuit (SSBC), which can be used to realize uniform SOC operation for full utilization of the battery capacity in proposed HCMC or any CMI inverter while keeping balanced three-phase operation. A sinusoidal PWM modulation technique is used to control power transferring between phases. Simulation results have been carried out to verify the performance of the proposed SSBC circuit of uniform three-phase SOC balancing

A Modulation Scheme for Floating Source Multilevel Inverter Topology with Increased Number of Output Levels

This paper presented and studied a new switching scheme for floating source multilevel inverters to produce more levels with the same number of switching devices. In the proposed scheme, the function of the dc sources, except the inner one, is to build up square wave or blocks that is close in the shape to the desired sinusoidal wave. The job of the inner switching devices is to increase the number of the levels to produce smother sinusoidal wave in the inverter output. This job can be done by adding or subtracting the value of the inner dc source to/from the blocks. The topology used in this paper is based on the conventional floating source multi-level inverter using two legs. This topology and modulation technique show substantial reduction in the total harmonics distortion when the modulation technique is the hybrid method. The performance of the proposed switching scheme in generating more levels has been evaluated by PSCAD/EMTDC simulation

A developed asymmetric mulitlevel inverter with lower number of components

In this paper, a new configuration for symmetrical and asymmetrical multilevel inverters is proposed. In asymmetric mode, different algorithms are suggested in order to determine the magnitudes of DC voltage sources. The merit of this topology to the conventional symmetric and asymmetric inverters is verified by the provided comparisons. This topology uses a lower number of power electronic devices such as switches, IGBTs, diodes, related gate driver circuits and DC voltage sources. Owing the lower amount of requirements, it has lower total costs and needs less installation area. Also the control strategy has less complexity. The proposed converter can generate all the desired output voltage levels with positive and negative values. To confirm the practicability of the proposed inverter, simulation and experimental results are provided which are in good agreements

A New Symmetric/Asymmetric Multilevel Inverter Based on Cascaded Connection of Sub-Multilevel Units Aiming less Switching Components and Total Blocked Voltage

In this paper, a new multilevel inverter is designed to improve the power and voltage quality, which contains a lesser number of switches in the specified voltage levels. The proposed inverter includes power electronic devices such as switches and diode, and DC inputs. In the proposed structure the desired output voltage can be produced by considering a series connection of a novel sub-multilevel module. This structure can be designed in both the symmetric and asymmetric topologies. The proposed structure has superior condition in terms of semiconductor switches and drivers count as well as switching loss. Additionally, the Total Blocked Voltage (TBV) of the proposed converter is compared with the conventional and the novel converters. This topology is studied by symmetric as well as asymmetric topologies through simulations in Matlab/Simulink environment as well as experiments by a laboratory prototype

A new scheme of symmetric multilevel inverter with reduced number of circuit devices

In this paper, a sophisticated configuration for symmetric multilevel voltage source inverters is proposed. In multilevel inverters, the costs, circuit size so installation space, complexness of control scheme and reliability are directly depended to the amount of circuit devices required. The provided comparison study among proposed inverter, CHB and recently introduced converters, validates that the proposed inverter reduces the requirements for circuit devices, including power semi-conductor switches, IGBTs, diodes, gate driver circuits and DC voltage sources. The given simulation results confirms the feasibleness of the projected modular structure. Also, to approve the practicality of the proposed inverter, a prototype of the proposed topology has been implemented. Finally simulation and experimental results are compared with one another and therefore the provided comparison shows that the obtained results are in sensible agreements

Design and Hardware Implementation Considerations of Modified Multilevel Cascaded H-Bridge Inverter for Photovoltaic System

Inverters are an essential part in many applications including photovoltaic generation. With the increasing penetration of renewable energy sources, the drive for efficient inverters is gaining more and more momentum. In this paper, output power quality, power loss, implementation complexity, cost, and relative advantages of the popular cascaded multilevel H-bridge inverter and a modified version of it are explored. An optimal number of levels and the optimal switching frequency for such inverters are investigated, and a five-level architecture is chosen considering the trade-offs. This inverter is driven by level shifted in-phase disposition pulse width modulation technique to reduce harmonics, which is chosen through deliberate testing of other advanced disposition pulse width modulation techniques. To reduce the harmonics further, the application of filters is investigated, and an LC filter is applied which provided appreciable results. This system is tested in MATLAB/Simulink and then implemented in hardware after design and testing in Proteus ISIS. The general cascaded multilevel H-bridge inverter design is also implemented in hardware to demonstrate a novel low-cost MOSFET driver build for this study. The hardware setups use MOSFETs as switching devices and low-cost ATmega microcontrollers for generating the switching pulses via level shifted in-phase disposition pulse width modulation. This implementation substantiated the effectiveness of the proposed design

REDUCED NUMBER OF SWITCHES FOR SEVEN LEVEL INVERTER

Multilevel inverters hold attractive features, which make them to be utilized in wide range of applications. But with increase in number of output levels, the number of semiconductor switches in the respective configurations increase which may lead to vast size and hikes the installation cost of the inverter. Here the project presents effective configurations for seven level inverter. A configuration is built with single DC voltage source with a series of capacitors, diodes, seven active switches including a H-bridge for generation of seven level output. Other configurations are built with three dc voltagge sources, six active switches and four dc voltage sourc es, five active switches. Multi carrier based Pulse Widt h Modulation technique is used for the switching of gate trigger circuitry. Computer aided simulation is done to validate the considered approach using MATLAB/SIM ULINK. The performance quality in terms of Total Harm onic Distortion of the considered multilevel inverter structures are compared with each other to obtain the effective topology for seven level output

Design, Optimization and Implementation of a High Frequency Link Multilevel Cascaded Inverter

This thesis presents a new concept of cascaded MLI (CMLI) device reduction by utilizing low and high frequency transformer link. Two CMLI topologies, symmetric and asymmetric are proposed. Compared with counterpart CMLI topologies available in the literatures, the proposed two inverter topologies in this thesis have the advantages of utilizing least number of electronic components without compromising overall performance particularly when a high number of levels is required in the output voltage waveform