Design of complex integrated systems based on networks-on-chip: Trading off performance, power and reliability

The steady advancement of microelectronics is associated with an escalating number of challenges for design engineers due to both the tiny dimensions and the enormous complexity of integrated systems. Against this background, this work deals with Network-On-Chip (NOC) as the emerging design paradigm to cope with diverse issues of nanotechnology. The detailed investigations within the chapters focus on the communication-centric aspects of multi-core-systems, whereas performance, power consumption as well as reliability are considered likewise as the essential design criteria

Energy-precision tradeoffs in the graphics pipeline

The energy consumption of a graphics processing unit (GPU) is an important factor in its design, whether for a server, desktop, or mobile device. Mobile products, such as smart phones, tablets, and laptop computers, rely on batteries to function; the less the demand for power is on these batteries, the longer they will last before needing to be recharged. GPUs used in servers and desktops, while not dependent on a battery for operation, are still limited by the efficiency of power supplies and heat dissipation techniques. In this dissertation, I propose to lower the energy consumption of GPUs by reducing the precision of floating-point arithmetic in the graphics pipeline and the data sent and stored on- and off-chip. The key idea behind this work is twofold: energy can be saved through a systematic and targeted reduction in the number of bits 1) computed and 2) communicated. Reducing the number of bits computed will necessarily reduce either the precision or range of a floating point number. I focus on saving energy by way of reducing precision, which can exploit the over-provisioning of bits in many stages of the graphics pipeline. Reducing the number of bits communicated takes several forms. First, I propose enhancements to existing compression schemes for off-chip buffers to save bandwidth. I also suggest a simple extension that exploits unused bits in reduced-precision data undergoing compression. Finally, I present techniques for saving energy in on-chip communication of reduced-precision data. By designing and simulating variable-precision arithmetic circuits with promising energy versus precision characteristics and tradeoffs, I have developed an energy model for GPUs. Using this model and my techniques, I have shown that significant savings (up to 70% in computation in the vertex and pixel shader stages) are possible by reducing the precision of the arithmetic. Further, my compression approaches have enabled improvements of 1.26x over past work, and a general-purpose compressor design has achieved bandwidth savings of 34%, 87%, and 65% for color, depth, and geometry data, respectively, which is competitive with past work. Lastly, an initial exploration in signal gating unused lines in on-chip buses has suggested savings of 13-48% for the tested applications' traffic from a multiprocessor's register file to its L1 cache

Cross-Layer Approaches for an Aging-Aware Design of Nanoscale Microprocessors

Thanks to aggressive scaling of transistor dimensions, computers have revolutionized our life. However, the increasing unreliability of devices fabricated in nanoscale technologies emerged as a major threat for the future success of computers. In particular, accelerated transistor aging is of great importance, as it reduces the lifetime of digital systems. This thesis addresses this challenge by proposing new methods to model, analyze and mitigate aging at microarchitecture-level and above

Yield-Aware Leakage Power Reduction of On-Chip SRAMs

Leakage power dissipation of on-chip static random access memories (SRAMs) constitutes a significant fraction of the total chip power consumption in state-of-the-art microprocessors and system-on-chips (SoCs). Scaling the supply voltage of SRAMs during idle periods is a simple yet effective technique to reduce their leakage power consumption. However, supply voltage scaling also results in the degradation of the cells’ robustness, and thus reduces their capability to retain data reliably. This is particularly resulting in the failure of an increasing number of cells that are already weakened by excessive process parameters variations and/or manufacturing imperfections in nano-meter technologies. Thus, with technology scaling, it is becoming increasingly challenging to maintain the yield while attempting to reduce the leakage power of SRAMs. This research focuses on characterizing the yield-leakage tradeoffs and developing novel techniques for a yield-aware leakage power reduction of SRAMs. We first demonstrate that new fault behaviors emerge with the introduction of a low-leakage standby mode to SRAMs. In particular, it is shown that there are some types of defects in SRAM cells that start to cause failures only when the drowsy mode is activated. These defects are not sensitized in the active operating mode, and thus escape the traditional March tests. Fault models for these newly observed fault behaviors are developed and described in this thesis. Then, a new low-complexity test algorithm, called March RAD, is proposed that is capable of detecting all the drowsy faults as well as the simple traditional faults. Extreme process parameters variations can also result in SRAM cells with very weak data-retention capability. The probability of such cells may be very rare in small memory arrays, however, in large arrays, their probability is magnified by the huge number of bit-cells integrated on a single chip. Hence, it is critical also to account for such extremal events while attempting to scale the supply voltage of SRAMs. To estimate the statistics of such rare events within a reasonable computational time, we have employed concepts from extreme value theory (EVT). This has enabled us to accurately model the tail of the cell failure probability distribution versus the supply voltage. Analytical models are then developed to characterize the yield-leakage tradeoffs in large modern SRAMs. It is shown that even a moderate scaling of the supply voltage of large SRAMs can potentially result in significant yield losses, especially in processes with highly fluctuating parameters. Thus, we have investigated the application of fault-tolerance techniques for a more efficient leakage reduction of SRAMs. These techniques allow for a more aggressive voltage scaling by providing tolerance to the failures that might occur during the sleep mode. The results show that in a 45-nm technology, assuming 10% variation in transistors threshold voltage, repairing a 64KB memory using only 8 redundant rows or incorporating single error correcting codes (ECCs) allows for ~90% leakage reduction while incurring only ~1% yield loss. The combination of redundancy and ECC, however, allows to reach the practical limits of leakage reduction in the analyzed benchmark, i.e., ~95%. Applying an identical standby voltage to all dies, regardless of their specific process parameters variations, can result in too many cell failures in some dies with heavily skewed process parameters, so that they may no longer be salvageable by the employed fault-tolerance techniques. To compensate for the inter-die variations, we have proposed to tune the standby voltage of each individual die to its corresponding minimum level, after manufacturing. A test algorithm is presented that can be used to identify the minimum applicable standby voltage to each individual memory die. A possible implementation of the proposed tuning technique is also demonstrated. Simulation results in a 45-nm predictive technology show that tuning standby voltage of SRAMs can enhance data-retention yield by an additional 10%−50%, depending on the severity of the variations

Integrated Guided-Wave Structures and Techniques for Millimeter-Wave and Terahertz Electronics and Photonics

RÉSUMÉ Pour faire face à la demande croissante en bande passante, les prochaines générations des systèmes sans fil et filaires devront exploiter la large gamme spectrale 100 GHz-1 Térahertz (THz) et au-delà. Cependant, les éléments constitutifs intégrés qui définiront les architectures et les normes des systèmes à très haute fréquence ne sont pas claires et généralement pas du tout disponible. Cette thèse contribue à ce nouveau défi en explorant de nouveaux concepts et techniques de transmission d’onde pour le développement des circuits intégrés et les systèmes électroniques et photoniques en ondes millimétriques (MMW) et THz. Les lignes de transmission sont les éléments constitutifs de tous les circuits électroniques et photoniques intégrés. En dépit d'une expansion substantielle des applications électroniques et photoniques vers les THz, la structure de base des lignes de transmission standard, mis au point dans les années 1950, n'a pas évolué. L'un des problèmes fondamentaux dans le développement de systèmes électroniques et photoniques intégré THz est les limites intrinsèques de ces lignes de transmission classiques. Les dispositifs à ondes progressives électro-optiques et optoélectroniques ont été conçus sur la base de ces lignes de transmission, et sont donc limités en débit en raison de la limitation des performances au spectre RF. Plusieurs tentatives ont été faites pour améliorer ces lignes de transmission. Cependant, la configuration structurelle inhérente du métal est toujours l'obstacle dominant qui impose un mode de fonctionnement particulier qui est sujette à l'atténuation et la dispersion à une fréquence plus élevée. Pour faire face aux problèmes mentionnés et pour répondre à ces défis technologiques contraignants, trois orientations sont traités dans cette thèse: électro-optique, micro-ondes et optique. Pour la première orientation, la ligne SIW est utilisée en tant que structure à onde progressive alternative d'un Modulateur EO sur polymère. Dans ce cas, la fréquence porteuse est déterminée par la fréquence de fonctionnement de la ligne SIW. Dans ce travail, la conception est faite pour un modulateur EO atteignant plus de 22% de la bande passante optique avec la fréquence centrale de 160 GHz.----------ABSTRACT In order to keep up with rising global demand for bandwidth, future generations of both wireless and wireline technology will need to exploit the spectral range over 100 GHz - 1 terahertz (THz) and beyond. However, the integrated building blocks that will well define such an ultra-high frequency system technology architecture and protocol are unclear and mostly unavailable. This dissertation set the stage in responding to this emerging challenge by exploring new guided wave structures, concepts and techniques for the development of millimeter-wave (mmW) and THz electronic and photonic integrated circuits and systems. Radiofrequency integrated circuits are the backbone of all modern computing and communication electronic and photonic networks and systems. Likewise, transmission lines are the most fundamental building blocks of all the electronic and photonics integrated circuits. In spite of a substantial expansion of electronic and photonic applications towards THz, the basic structure of traditional transmission lines, developed in the 1950s, has not been modified or evolved. One of the fundamental bottlenecks in the development of THz integrated electronic and photonic systems has been the inherent limitations of those conventional transmission lines. The traveling-wave electro-optic and opto-electronic devices have been made based on those transmission lines, and are therefore limited in speed because of the RF spectrum performance limitations. Several attempts have been made to improve those transmission lines. However, the inherent structural configuration is still the dominant obstacle that dictates a particular operating mode that is prone to attenuation and dispersion at higher frequencies. To tackle those mentioned problems and to respond to those constraining technological challenges, three research orientations are considered in this PhD thesis: electro-optic, microwave, and optics. For the first orientation, SIW (substrate integrated waveguide) is used as an alternative traveling-wave structure of a polymer EO modulator. In this case, the carrier frequency is determined by the SIW frequency of operation. The design in this work is completed for an EO modulator with the center frequency of 160 GHz achieving more than 22% optical bandwidth

Advanced Modulation and Coding Technology Conference

The objectives, approach, and status of all current LeRC-sponsored industry contracts and university grants are presented. The following topics are covered: (1) the LeRC Space Communications Program, and Advanced Modulation and Coding Projects; (2) the status of four contracts for development of proof-of-concept modems; (3) modulation and coding work done under three university grants, two small business innovation research contracts, and two demonstration model hardware development contracts; and (4) technology needs and opportunities for future missions

Bipolar electrochemistry for enrichment, separations, and membraneless electrochemically mediated desalination

Developments in bipolar electrochemistry for the simultaneous separation and enrichment of charged species and membraneless electrochemically mediated desalination (EMD) are presented. Each of these techniques requires an electrochemically generated local electric field within a microchannel and control over bulk fluid flow. In addition to bipolar electrochemical studies, investigations of ion depletion zone formation and EMD in a two-electrode microelectrochemical cell are presented. The dual-channel bipolar electrode (BPE) configuration is employed for the simultaneous enrichment and separation of anions and cations within a single microchannel at an ion depletion zone generated by buffer neutralization. Moreover, this experimental design is also used to generate an ion depletion zone and associated electric field gradient by Cl⁻ oxidation, where we demonstrate partial seawater desalination without the need for a physical membrane. Expanding upon the fundamentals of BPE focusing, we demonstrate proof-of-concept biomolecule separation and enrichment. Moreover, without the need for a direct external electrical connection, one hundred BPEs are operated simultaneously in parallel to enrich multiple analyte bands. Metal deposition at a BPE is used to mediate BPE focusing. Ion depletion zones arising from Cl⁻ oxidation are investigated by making axial electric field measurements while varying key experimental parameters affecting ion depletion zone formation, location, and strength. We investigate the capabilities of EMD by modifying the electrode design to increase the local electric field strength in an effort to increase the percentage of salt rejection. We also examine the possibility to lower, or even eliminate the electrical energy requirements of EMD by driving Cl⁻ oxidation photoelectrochemically. Lastly, on-line capacitively coupled contactless conductivity measurements are presented to rapidly and reliably quantify ion separation for EMD.Chemistr

Modern Applications in Optics and Photonics: From Sensing and Analytics to Communication

Optics and photonics are among the key technologies of the 21st century, and offer potential for novel applications in areas such as sensing and spectroscopy, analytics, monitoring, biomedical imaging/diagnostics, and optical communication technology. The high degree of control over light fields, together with the capabilities of modern processing and integration technology, enables new optical measurement systems with enhanced functionality and sensitivity. They are attractive for a range of applications that were previously inaccessible. This Special Issue aims to provide an overview of some of the most advanced application areas in optics and photonics and indicate the broad potential for the future

2022 roadmap on neuromorphic computing and engineering

Modern computation based on von Neumann architecture is now a mature cutting-edge science. In the von Neumann architecture, processing and memory units are implemented as separate blocks interchanging data intensively and continuously. This data transfer is responsible for a large part of the power consumption. The next generation computer technology is expected to solve problems at the exascale with 10$^{18}$ calculations each second. Even though these future computers will be incredibly powerful, if they are based on von Neumann type architectures, they will consume between 20 and 30 megawatts of power and will not have intrinsic physically built-in capabilities to learn or deal with complex data as our brain does. These needs can be addressed by neuromorphic computing systems which are inspired by the biological concepts of the human brain. This new generation of computers has the potential to be used for the storage and processing of large amounts of digital information with much lower power consumption than conventional processors. Among their potential future applications, an important niche is moving the control from data centers to edge devices. The aim of this roadmap is to present a snapshot of the present state of neuromorphic technology and provide an opinion on the challenges and opportunities that the future holds in the major areas of neuromorphic technology, namely materials, devices, neuromorphic circuits, neuromorphic algorithms, applications, and ethics. The roadmap is a collection of perspectives where leading researchers in the neuromorphic community provide their own view about the current state and the future challenges for each research area. We hope that this roadmap will be a useful resource by providing a concise yet comprehensive introduction to readers outside this field, for those who are just entering the field, as well as providing future perspectives for those who are well established in the neuromorphic computing community