액정폴리머를 기반의 소형, 안구밀착형, 장기안정적인 인공망막장치

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2015. 8. 김성준.A novel retinal prosthetic device was developed using liquid crystal polymer (LCP) to address the problems associated with conventional metal- and polymer-based devices: the hermetic metal package is bulky, heavy and labor-intensive, whereas a thin, flexible and MEMS-compatible polymer-based system is not durable enough for chronic implantation. Exploiting the advantageous properties of LCP such as a low moisture absorption rate, thermo-bonding and thermo-forming, a small, light-weight, long-term reliable retinal prosthesis was fabricated that can be conformally attached on the eye-surface. A LCP fabrication process using monolithic integration and conformal deformation was established enabling miniaturization and a batch manufacturing process as well as eliminating the need for feed-through technology. The fabricated 16-channels LCP-based retinal implant had 14 mm-diameter with the maximum thickness of 1.4 mm and weight of 0.4 g and could be operated wirelessly up to 16 mm of distance in the air. The long-term reliability of the all-LCP retinal device was evaluated in vitro as well as in vivo. Because an all-polymer implant introduces intrinsic gas permeation for which the traditional helium leak test for metallic packages was not designed to quantify, a new set of reliability tests were designed and carried out specifically for all-polymer implants. Moisture ingress through various pathways were classified into polymer surface, polymer-polymer and polymer-metal adhesions each of which were quantitatively investigated by analytic calculation, in vitro aging test of electrode part and package part, respectively. The functionality and long-term implantation stability of the device was verified through in vivo animal experiments by measuring the cortical potential and monitoring implanted dummy devices for more than a year, respectively. Samples of the LCP electrodes array failed after 114 days in 87°C salin as a result of water penetration through the LCP-metal interface. An eye-confirmable LCP package survived more than 35 days in an accelerated condition at 87°C. The in vivo results confirmed that no adverse effects around the retina were observed after implantation of the device for more than a year.ABSTRACT i Contents iv List of Figures xi List of Tables xxi Chapter 1 : Introduction 1 1.1. Neuroprosthetic devices 1 1.2. Retinal prosthesis 2 1.2.1. Concept 2 1.2.2. Three approaches 3 1.2.3. Camera vs. Photodiode 4 1.3. Conventional devices 5 1.4. Liquid Crystal Polymer (LCP) 7 1.4.1. Low moisture absorption and permeability 9 1.4.2. Thermoplastic property 9 1.4.3. Compatibility with MEMS technologies 10 1.4.4. RF characteristics 10 1.5. LCP-based retinal prosthesis 11 1.6. Long-term reliability 12 1.7. Dissertation outline 14 Chapter 2: Methods 16 2.1. System Overview 16 2.2. Microfabrication on LCP 18 2.2.1. Limitations of the previous microfabrication technique on LCP 19 2.2.2. Improved LCP-based microfabrication 22 2.2.2.1. Electroplated micro-patterning 23 2.2.2.2. Laser-thinning for higher flexibility 24 2.2.2.3. Laser-ablation for site opening 25 2.3. All-LCP Monolithic Fabrication 26 2.3.1. Multilayered integration 29 2.3.1.1. Electrical components 29 2.3.1.2. Thermal lamination 32 2.3.1.3. Layer configuration 34 2.3.2. Thermal deformation 35 2.3.2.1. Deformation process 35 2.3.2.2. Wavy lines for stretchability 36 2.3.2.3. Electrical properties of the deformed coil 40 2.3.3. Circuit Assembly 40 2.3.3.1. Stimulation ASIC 40 2.3.3.2. Surrounding circuitries 41 2.3.4. Packaging 43 2.3.5. Laser Machining 44 2.4. Device characterization 44 2.4.1. Transmitter Circuit and Wireless Operation 45 2.4.1.1. Transmitter circuit 45 2.4.1.2. Transmitter coil 46 2.4.1.3. Wireless operation test 46 2.4.2. Electrochemical measurements 48 2.5. Long-term reliability tests in vitro 49 2.5.1. Failure mechanisms of an all-LCP device 49 2.5.2. Analytic calculation 51 2.5.3. Long-term reliability tests in accelerated environment 55 2.5.3.1. Long-term reliability of electrode array 55 2.5.3.2. Long-term reliability of package 57 2.5.3.3. Long-term reliability of complete device 58 2.5.4. Long-term electrochemical stability 59 2.6. Acute and Chronic Evaluation in vivo 60 2.6.1. Surgical implantation 60 2.6.2. Acute functionality test 62 2.6.3. Long-term implantation stability 63 Chapter 3: Results 64 3.1. Microfabrication on LCP 64 3.1.1. Electroplated micro-patterning 64 3.1.2. Laser-ablation for site opening 67 3.1.3. Laser-thinning for higher flexibility 69 3.2. All-LCP Monolithic fabrication 71 3.2.1. Multilayered integration 71 3.2.2. Thermal deformation 73 3.2.2.1. Deformation results 73 3.2.2.2. Wavy lines for stretchability 74 3.2.2.3. Effect on the electrical properties 74 3.2.3. Circuit assembly 76 3.2.4. Packaging 77 3.2.5. Laser machining 79 3.3. Device Characterization 80 3.3.1. General specifications 81 3.3.2. Transmitter circuit and coil 83 3.3.3. Wireless operation 83 3.3.4. Electrochemical measurements 84 3.4. Long-term reliability tests in vitro 86 3.4.1. Analytic calculation 87 3.4.2. Long-term reliability tests in accelerated condition 90 3.4.2.1. Long-term reliability of electrode arrays 90 3.4.2.2. Long-term reliability of package 92 3.4.2.3. Long-term reliability of complete device 93 3.4.3. Long-term Electrochemical stability 93 3.5. Acute and chronic evaluation in vivo 95 3.5.1. Surgical implantation 95 3.5.2. Acute functionality test 96 3.5.3. Long-term implantation stability 97 Chapter 4: Discussion 100 4.1. Comparison with conventional devices 100 4.2. Potential applications 102 4.3. Opportunities for further improvements 102 4.4. Long-term reliability 104 Chapter 5: Conclusion 108 Reference 110 국문초록 118 감사의 글 121Docto

Advanced analog layout design automation in compliance with density uniformity

To fabricate a reliable integrated circuit chip, foundries follow specific design rules and layout processing techniques. One of the parameters, which affect circuit performance and final electronic product quality, is the variation of thickness for each semiconductor layer within the fabricated chips. The thickness is closely dependent on the density of geometric features on that layer. Therefore, to ensure consistent thickness, foundries normally have to seriously control distribution of the feature density on each layer by using post-processing operations. In this research, the methods of controlling feature density distribution on different layers of an analog layout during the process of layout migration from an old technology to a new one or updated design specifications in the same technology have been investigated. We aim to achieve density-uniformity-aware layout retargeting for facilitating manufacturing process in the advanced technologies. This can offer an advantage right to the design stage for the designers to evaluate the effects of applying density uniformity to their drafted layouts, which are otherwise usually done by the foundries at the final manufacturing stage without considering circuit performance. Layout modification for density uniformity includes component position change and size modification, which may induce crosstalk noise caused by extra parasitic capacitance. To effectively control this effect, we have also investigated and proposed a simple yet accurate analytic method to model the parasitic capacitance on multi-layer VLSI chips. Supported by this capacitance modeling research, a unique methodology to deal with density-uniformity-aware analog layout retargeting with the capability of parasitic capacitance control has been presented. The proposed operations include layout geometry position rearrangement, interconnect size modification, and extra dummy fill insertion for enhancing layout density uniformity. All of these operations are holistically coordinated by a linear programming optimization scheme. The experimental results demonstrate the efficacy of the proposed methodology compared to the popular digital solutions in terms of minimum density variation and acute parasitic capacitance control

Multi-gigabit CMOS analog-to-digital converter and mixed-signal demodulator for low-power millimeter-wave communication systems

The objective of the research is to develop high-speed ADCs and mixed-signal demodulator for multi-gigabit communication systems using millimeter-wave frequency bands in standard CMOS technology. With rapid advancements in semiconductor technologies, mobile communication devices have become more versatile, portable, and inexpensive over the last few decades. However, plagued by the short lifetime of batteries, low power consumption has become an extremely important specification in developing mobile communication devices. The ever-expanding demand of consumers to access and share information ubiquitously at faster speeds requires higher throughputs, increased signal-processing functionalities at lower power and lower costs. In today’s technology, high-speed signal processing and data converters are incorporated in almost all modern multi-gigabit communication systems. They are key enabling technologies for scalable digital design and implementation of baseband signal processors. Ultimately, the merits of a high performance mixed-signal receiver, such as data rate, sensitivity, signal dynamic range, bit-error rate, and power consumption, are directly related to the quality of the embedded ADCs. Therefore, this dissertation focuses on the analysis and design of high-speed ADCs and a novel broadband mixed-signal demodulator with a fully-integrated DSP composed of low-cost CMOS circuitry. The proposed system features a novel dual-mode solution to demodulate multi-gigabit BPSK and ASK signals. This approach reduces the resolution requirement of high-speed ADCs, while dramatically reducing its power consumption for multi-gigabit wireless communication systems.PhDGee-Kung Chang - Committee Chair; Chang-Ho Lee - Committee Member; Geoffrey Ye Li - Committee Member; Paul A. Kohl - Committee Member; Shyh-Chiang Shen - Committee Membe

A Low-Power Silicon-Photomultiplier Readout ASIC for the CALICE Analog Hadronic Calorimeter

The future e + e − collider experiments, such as the international linear collider, provide precise measurements of the heavy bosons and serve as excellent tests of the underlying fundamental physics. To reconstruct these bosons with an unprecedented resolution from their multi-jet final states, a detector system employing the particle flow approach has been proposed, requesting calorimeters with imaging capabilities. The analog hadron calorimeter based on the SiPM-on-tile technology is one of the highly granular candidates of the imaging calorimeters. To achieve the compactness, the silicon-photomultiplier (SiPM) readout electronics require a low-power monolithic solution. This thesis presents the design of such an application-specific integrated circuit (ASIC) for the charge and timing readout of the SiPMs. The ASIC provides precise charge measurement over a large dynamic range with auto-triggering and local zero-suppression functionalities. The charge and timing information are digitized using channel-wise analog-to-digital and time-to-digital converters, providing a fully integrated solution for the SiPM readout. Dedicated to the analog hadron calorimeter, the power-pulsing technique is applied to the full chip to meet the stringent power consumption requirement. This work also initializes the commissioning of the calorimeter layer with the use of the designed ASIC. An automatic calibration procedure has been developed to optimized the configuration settings for the chip. The new calorimeter base unit with the designed ASIC has been produced and its functionality has been tested

Design of Resistive Synaptic Devices and Array Architectures for Neuromorphic Computing

abstract: Over the past few decades, the silicon complementary-metal-oxide-semiconductor (CMOS) technology has been greatly scaled down to achieve higher performance, density and lower power consumption. As the device dimension is approaching its fundamental physical limit, there is an increasing demand for exploration of emerging devices with distinct operating principles from conventional CMOS. In recent years, many efforts have been devoted in the research of next-generation emerging non-volatile memory (eNVM) technologies, such as resistive random access memory (RRAM) and phase change memory (PCM), to replace conventional digital memories (e.g. SRAM) for implementation of synapses in large-scale neuromorphic computing systems. Essentially being compact and “analog”, these eNVM devices in a crossbar array can compute vector-matrix multiplication in parallel, significantly speeding up the machine/deep learning algorithms. However, non-ideal eNVM device and array properties may hamper the learning accuracy. To quantify their impact, the sparse coding algorithm was used as a starting point, where the strategies to remedy the accuracy loss were proposed, and the circuit-level design trade-offs were also analyzed. At architecture level, the parallel “pseudo-crossbar” array to prevent the write disturbance issue was presented. The peripheral circuits to support various parallel array architectures were also designed. One key component is the read circuit that employs the principle of integrate-and-fire neuron model to convert the analog column current to digital output. However, the read circuit is not area-efficient, which was proposed to be replaced with a compact two-terminal oscillation neuron device that exhibits metal-insulator-transition phenomenon. To facilitate the design exploration, a circuit-level macro simulator “NeuroSim” was developed in C++ to estimate the area, latency, energy and leakage power of various neuromorphic architectures. NeuroSim provides a wide variety of design options at the circuit/device level. NeuroSim can be used alone or as a supporting module to provide circuit-level performance estimation in neural network algorithms. A 2-layer multilayer perceptron (MLP) simulator with integration of NeuroSim was demonstrated to evaluate both the learning accuracy and circuit-level performance metrics for the online learning and offline classification, as well as to study the impact of eNVM reliability issues such as data retention and write endurance on the learning performance.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

DFM Techniques for the Detection and Mitigation of Hotspots in Nanometer Technology

With the continuous scaling down of dimensions in advanced technology nodes, process variations are getting worse for each new node. Process variations have a large influence on the quality and yield of the designed and manufactured circuits. There is a growing need for fast and efficient techniques to characterize and mitigate the effects of different sources of process variations on the design's performance and yield. In this thesis we have studied the various sources of systematic process variations and their effects on the circuit, and the various methodologies to combat systematic process variation in the design space. We developed abstract and accurate process variability models, that would model systematic intra-die variations. The models convert the variation in process into variation in electrical parameters of devices and hence variation in circuit performance (timing and leakage) without the need for circuit simulation. And as the analysis and mitigation techniques are studied in different levels of the design ow, we proposed a flow for combating the systematic process variation in nano-meter CMOS technology. By calculating the effects of variability on the electrical performance of circuits we can gauge the importance of the accurate analysis and model-driven corrections. We presented an automated framework that allows the integration of circuit analysis with process variability modeling to optimize the computer intense process simulation steps and optimize the usage of variation mitigation techniques. And we used the results obtained from using this framework to develop a relation between layout regularity and resilience of the devices to process variation. We used these findings to develop a novel technique for fast detection of critical failures (hotspots) resulting from process variation. We showed that our approach is superior to other published techniques in both accuracy and predictability. Finally, we presented an automated method for fixing the lithography hotspots. Our method showed success rate of 99% in fixing hotspots

Development of a Detector Control System Chip

Der Large Hadron Collider (LHC) am CERN wird bis 2026 zum High-Luminosity LHC ausgebaut. Diese Erweiterung hat zum Ziel höhere Intensitäten bei den Kollisionen zu erreichen um die gesammelte Luminosität um einen Faktor 10 zu erhöhen. Mit dem grösseren Datensatz können die Eigenschaften des Standard Models der Teilchenphysik genauer vermessen werden. Die Experimente müssen dafür aktualisiert und aufgerüstet werden. Beim ATLAS Experiment wird der komplette innere Detektor für den Betrieb am High-Luminosity LHC mit einem neuen Silizium-Spurdetektor ersetzt. Dieser, ATLAS ITk Detektor genannt, besteht aus mehreren Lagen mit Pixel- und Streifensensoren. Für den ITk Pixeldetektor wird erstmals auch eine serielle Stromversorgung an einem LHC Experiment verwendet. Die serielle Versorgung hat den Vorteil, dass Leitungen und dadurch Material eingespart werden kann. Jedoch gibt es auch Risiken und neue Entwicklungen werden benötigt. Das Detektorkontrollsystem (DCS) hat die Aufgabe den Detektor und seinen Zustand zu überwachen. Das DCS kontrolliert auch den Betrieb des Detektors. Eine Integrierte Schaltung wurde speziell dazu entwickelt. Dieser Pixel Serial Power & Protection (PSPP) genannte Chip misst die Temperatur und Spannung von einem Modul in einer seriellen Versorgungskette. Weiter hat der Chip einen Bypass-Transistor, welcher das Modul kurzschliessen und damit deaktivieren kann. Das erlaubt es einzelne Module in der seriellen Versorgungskette zu steuern, während die anderen Module weiterhin funktionieren. Die Aktivierung des Bypasses kann automatisch erfolgen, sollte die Temperatur oder Spannung des Moduls zu gross werden. Auf Basis eines existierenden Prototyps wurden während dieser Arbeit weitere Versionen des PSPP entwickelt. Diese beinhalten alle benötigten Funktionen und können einen Strom von 8 A schalten. Der entwickelte PSPP wurde bis zu einer totalen ionisierenden Dosis von 800 Mrad erfolgreich getestet. Weiter wurden Tests der Resistenz gegenüber strahlenbasierten Bit-Flips durchgeführt. Es wurde ein Wirkungsquerschnitt kleiner 1.7 × 10⁻¹⁷ cm² gemessen. Ein Chip wurde auch in einer Klimakammer bei Temperaturen zwischen (0 und 60) °C während 42 Tagen erfolgreich betrieben. Während dieses Dauertests wurden keine Fehlfunktionen beobachtet. Der PSPP wurde ausserdem in einem Systemtest mit Sensormodulen und realistischer mechanischer Struktur eingesetzt. Die Funktion des PSPPs war hilfreich bei der Inbetriebnahme und Fehlersuche. Die automatische Bypass-Aktivierung bewahrte die Module vor Schäden. Mit Hilfe der vom PSPP gemessenen Daten wurde die Spezifikation der seriellen Versorgungskette verbessert.The Large Hadron Collider (LHC) at CERN will be updated to the High-Luminosity LHC by 2026. The goal of this update is to achieve higher intensities in the collisions and collect ten times more luminosity than with the LHC. This gives higher statistics to measure with greater precision the parameters of the standard model in particle physics. The ATLAS experiment will receive a completely new inner tracker for operation at the High-Luminosity LHC. This ATLAS ITk detector is a full silicon tracking detector with pixel and strip sensors. A serial power approach is foreseen for the ITk Pixel detector. This reduces the number of services and material, however, has also risks and new challenges. The task of the detector control system (DCS) is to monitor the health of the experiment and control the operation. An integrated circuit was developed for this task. The so-called pixel serial power & protection (PSPP) chip measures the voltage and temperature of a module in the serial power chain. Additionally, it includes a bypass transistor to deactivate a single module if necessary. The bypass is activated automatically in case of over-temperature or over-voltage. This gives full control over each module and allows to recover a serial power chain in case of a faulty module. Based on an existing prototype, new versions of the PSPP were developed for this thesis. They include all required functionalities and can switch a current of 8 A. The developed prototype is functional to a total integrated dose of 800 Mrad, which was tested in X-Ray irradiations. Further, tests were performed to verify the protection against single event upsets causing bit flips in the internal registers. The cross-section of the triplicated registers in the PSPP was measured with a proton test beam and is smaller than 1.7 × 10⁻¹⁷ cm² . The PSPP prototype successfully resisted temperatures between (0 and 60) °C in a 42-day long climate chamber test. No failure was observed. A system test with prototype modules was built at CERN to verify the concept of the serial power chain. This used realistic services and mechanical structures. The PSPP chip was included in the system test and proofed to be very useful during commissioning and debugging. The bypass and its protection function prevented damage to detector modules. The PSPP delivered useful monitoring data to refine the requirements of the serial power chain