Two improved methods for testing ADC parametric faults by digital input signals

In this paper, two improved methods are presented extending our previous work. The first one improves the results by adjusting the voltage levels of the input pulse wave stimulus. Compared with the sine wave input stimulus, the four-level pulse wave can detect even more faulty cases with the offset faults. The second one improves the results by calculating the similarity of the output spectra between the golden devices and the DUTs. Compared with the previous method [10], it is less sensitive to the jitter and the change of the rise/fall time of the input pulse wave stimulus. In these two methods, a number of golden devices are tested at first to obtain the fault-free range. At last, a signature result is obtained from both methods. It can filter out the faulty devices in a quick way before testing the specific values of the conventional dynamic and static parameters

Jitter and Decision-level Noise Separation in A/D Converters

Gaussian aperture jitter leads to a reduced SNR of A/D converters. Also other noise sources, faults and nonlinearities affect the digital output signal. A measurement setup for a new off-chip diagnosis method, which systematically separates the jitter-induced errors from the errors caused by these other factors, is described. Deterministic errors are removed via a subtracting technique. High-level ADC simulations and measurements have been carried out to determine relations between the size of the jitter or decision-level noise and the remaining random errors. By carrying out two tests at two different input frequencies and using the simulation results, errors induced by decision-level noise can be remove

Readout for intersatellite laser interferometry: Measuring low frequency phase fluctuations of HF signals with microradian precision

Precision phase readout of optical beat note signals is one of the core techniques required for intersatellite laser interferometry. Future space based gravitational wave detectors like eLISA require such a readout over a wide range of MHz frequencies, due to orbit induced Doppler shifts, with a precision in the order of $\mu \textrm{rad}/\sqrt{\textrm{Hz}}$ at frequencies between $0.1\,\textrm{mHz}$ and $1\,\textrm{Hz}$. In this paper, we present phase readout systems, so-called phasemeters, that are able to achieve such precisions and we discuss various means that have been employed to reduce noise in the analogue circuit domain and during digitisation. We also discuss the influence of some non-linear noise sources in the analogue domain of such phasemeters. And finally, we present the performance that was achieved during testing of the elegant breadboard model of the LISA phasemeter, that was developed in the scope of an ESA technology development activity.Comment: submitted to Review of Scientific Instruments on April 30th 201

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin