Contribución al modelado y diseño de moduladores sigma-delta en tiempo continuo de baja relación de sobremuestreo y bajo consumo de potencia

Continuous-Time Sigma-Delta modulators are often employed as analog-to-digital converters. These modulators are an attractive approach to implement high-speed converters in VLSI systems because they have low sensitivity to circuit imperfections compared to other solutions. This work is a contribution to the analysis, modelling and design of high-speed Continuous-Time Sigma-Delta modulators. The resolution and the stability of these modulators are limited by two main factors, excess-loop delay and sampling uncertainty. Both factors, among others, have been carefully analysed and modelled. A new design methodology is also proposed. It can be used to get an optimum high-speed Continuous-Time Sigma-Delta modulator in terms of dynamic range, stability and sensitivity to sampling uncertainty. Based on the proposed design methodology, a software tool that covers the main steps has been developed. The methodology has been proved by using the tool in designing a 30 Megabits-per-second Continuous-Time Sigma-Delta modulator with 11-bits of dynamic range. The modulator has been integrated in a 0.13-µm CMOS technology and it has a measured peak SNR of 62.5dB

Parallel Implementation of a Real-Time High Dynamic Range Video System

Abstract. This article describes the use of the parallel processing capabilities of a graphics chip to increase the processing speed of a high dynamic range (HDR) video system. The basis is an existing HDR video system that produces each frame from a sequence of regular images taken in quick succession under varying exposure settings. The image sequence is processed in a pipeline consisting of: shutter speeds selection, capturing, color space conversion, image registration, HDR stitching, and tone mapping. This article identifies bottlenecks in the pipeline and describes modifications to the algorithms that are necessary to enable parallel processing. Time-critical steps are processed on a graphics processing unit (GPU). The resulting processing time is evaluated and compared to the original sequential code. The creation of an HDR video frame is sped up by a factor of 15 on the average

Fourth Aircraft Interior Noise Workshop

The fourth in a series of NASA/SAE Interior Noise Workshops was held on May 19 and 20, 1992. The theme of the workshop was new technology and applications for aircraft noise with emphasis on source noise prediction; cabin noise prediction; cabin noise control, including active and passive methods; and cabin interior noise procedures. This report is a compilation of the presentations made at the meeting which addressed the above issues

Wireless wire - ultra-low-power and high-data-rate wireless communication systems

With the rapid development of communication technologies, wireless personal-area communication systems gain momentum and become increasingly important. When the market gets gradually saturated and the technology becomes much more mature, new demands on higher throughput push the wireless communication further into the high-frequency and high-data-rate direction. For example, in the IEEE 802.15.3c standard, a 60-GHz physical layer is specified, which occupies the unlicensed 57 to 64 GHz band and supports gigabit links for applications such as wireless downloading and data streaming. Along with the progress, however, both wireless protocols and physical systems and devices start to become very complex. Due to the limited cut-off frequency of the technology and high parasitic and noise levels at high frequency bands, the power consumption of these systems, especially of the RF front-ends, increases significantly. The reason behind this is that RF performance does not scale with technology at the same rate as digital baseband circuits. Based on the challenges encountered, the wireless-wire system is proposed for the millimeter wave high-data-rate communication. In this system, beamsteering directional communication front-ends are used, which confine the RF power within a narrow beam and increase the level of the equivalent isotropic radiation power by a factor equal to the number of antenna elements. Since extra gain is obtained from the antenna beamsteering, less front-end gain is required, which will reduce the power consumption accordingly. Besides, the narrow beam also reduces the interference level to other nodes. In order to minimize the system average power consumption, an ultra-low power asynchronous duty-cycled wake-up receiver is added to listen to the channel and control the communication modes. The main receiver is switched on by the wake-up receiver only when the communication is identified while in other cases it will always be in sleep mode with virtually no power consumed. Before transmitting the payload, the event-triggered transmitter will send a wake-up beacon to the wake-up receiver. As long as the wake-up beacon is longer than one cycle of the wake-up receiver, it can be captured and identified. Furthermore, by adopting a frequency-sweeping injection locking oscillator, the wake-up receiver is able to achieve good sensitivity, low latency and wide bandwidth simultaneously. In this way, high-data-rate communication can be achieved with ultra-low average power consumption. System power optimization is achieved by optimizing the antenna number, data rate, modulation scheme, transceiver architecture, and transceiver circuitries with regards to particular application scenarios. Cross-layer power optimization is performed as well. In order to verify the most critical elements of this new approach, a W-band injection-locked oscillator and the wake-up receiver have been designed and implemented in standard TSMC 65-nm CMOS technology. It can be seen from the measurement results that the wake-up receiver is able to achieve about -60 dBm sensitivity, 10 mW peak power consumption and 8.5 µs worst-case latency simultaneously. When applying a duty-cycling scheme, the average power of the wake-up receiver becomes lower than 10 µW if the event frequency is 1000 times/day, which matches battery-based or energy harvesting-based wireless applications. A 4-path phased-array main receiver is simulated working with 1 Gbps data rate and on-off-keying modulation. The average power consumption is 10 µW with 10 Gb communication data per day

Spectral Efficiency Analysis of Filter Bank Multi‐Carrier (FBMC)‐ Based 5G Networks with Estimated Channel State Information (CSI)

Filter bank multi‐carrier (FBMC) modulation, as a potential candidate for physical data communication in the fifth generation (5G) wireless networks, has been widely investigated. This chapter focuses on the spectral efficiency analysis of FBMC‐based cognitive radio (CR) systems, and spectral efficiency comparison is conducted with another three types of multi‐carrier modulations: orthogonal frequency division multiplexing (OFDM), generalized frequency division multiplexing (GFDM), and universal‐filtered multi‐carrier (UFMC). In order to well evaluate and compare the spectral efficiency, we propose two resource allocation (RA) algorithms for single‐cell and two‐cell CR systems, respectively. In the single‐cell system, the RA algorithm is divided into two sequential steps, which incorporate subcarrier assignment and power allocation. In the two‐cell system, a noncooperative game is formulated and the multiple access channel (MAC) technique assists to solve the RA problem. The channel state information (CSI) between CR users and licensed users cannot be precisely known in practice, and thus, an estimated CSI is considered by defining a prescribed outage probability of licensed systems. Numerical results show that FBMC can achieve the highest channel capacity compared with another three waveforms