Design and Implementation of FPGA based linear All Digital Phase-Locked Loop for Signal Processing Applications

This project presents a linear all-digital phase locked loop based on FPGA. In this ADPLL the phase detection system is realized by generating an analytic signal using a compact implementation of Hilbert transform and then simply computing the instantaneous phase using CORDIC algorithm in vectoring mode of operation. A 16-bit pipelined CORDIC algorithm is employed in order to obtain the phase information of the signal. All the components used in this phase detection system are realized as digital discrete time components. This design does not involve any class of multipliers thus reducing the complexity of the design. The loop filter of the ADPLL has been designed using PI controller which has a low pass behavior and is used to discard the higher order harmonics of the error signal. The CORDIC algorithm in its rotation mode of operation is used to compute sinusoidal values for the DDS. The ADPLL model has been implemented using Xilinx ISE 12.3 and ModelSim PE Student Edition 10.1a. The ADPLL model describes a novel method of implementation of CORDIC algorithm for the DDS system. This ADPLL model basically used for synchronization of closed loop RF control signals in a heavy ion particle accelerator can be implemented even in an ASIC which can be seen with a more general use for many a applications in the daily life

Symbol Synchronization for SDR Using a Polyphase Filterbank Based on an FPGA

This paper is devoted to the proposal of a highly efficient symbol synchronization subsystem for Software Defined Radio. The proposed feedback phase-locked loop timing synchronizer is suitable for parallel implementation on an FPGA. The polyphase FIR filter simultaneously performs matched-filtering and arbitrary interpolation between acquired samples. Determination of the proper sampling instant is achieved by selecting a suitable polyphase filterbank using a derived index. This index is determined based on the output either the Zero-Crossing or Gardner Timing Error Detector. The paper will extensively focus on simulation of the proposed synchronization system. On the basis of this simulation, a complete, fully pipelined VHDL description model is created. This model is composed of a fully parallel polyphase filterbank based on distributed arithmetic, timing error detector and interpolation control block. Finally, RTL synthesis on an Altera Cyclone IV FPGA is presented and resource utilization in comparison with a conventional model is analyzed

Synchronization of a WDM Packet-Switched Slotted Ring

In this paper, we present two different strategies of slot synchronization in wavelength-division-multiplexing (WDM) packet-switched slotted-ring networks. Emphasis is given to the architecture behind the WDM Optical Network Demonstrator over Rings (WONDER) project, which is based on tunable transmitters and fixed receivers. The WONDER experimental prototype is currently being developed at the laboratories of Politecnico di Torino. In the former strategy, a slotsynchronization signal is transmitted by the master station on a dedicated control wavelength; in the latter, slave nodes achieve slot synchronization aligning on data packets that are received from the master. The performance of both synchronization strategies, particularly in terms of packet-collision probability, was evaluated by simulation. The technique based on transmitting a timing signal on a dedicated control wavelength achieves better performance, although it is more expensive due to the need for an additional wavelength. However, the technique based on aligning data packets that are received from the master, despite attaining lower timing stability, still deserves further study, particularly if limiting the number of wavelengths and receivers is a major requirement. Some experimental results, which were measured on the WONDER prototype, are also shown. Measurement results, together with theoretical findings, demonstrate the good synchronization performance of the prototype

Synchronization and Characterization of an Ultra-Short Laser for Photoemission and Electron-Beam Diagnostics Studies at a Radio Frequency Photoinjector

A commercially-available titanium-sapphire laser system has recently been installed at the Fermilab A0 photoinjector laboratory in support of photoemission and electron beam diagnostics studies. The laser system is synchronized to both the 1.3-GHz master oscillator and a 1-Hz signal use to trigger the radiofrequency system and instrumentation acquisition. The synchronization scheme and performance are detailed. Long-term temporal and intensity drifts are identified and actively suppressed to within 1 ps and 1.5%, respectively. Measurement and optimization of the laser's temporal profile are accomplished using frequency-resolved optical gating.Comment: 16 pages, 17 figures, Preprint submitted to Elsevie

An Efficient Beam Steerable Antenna Array Concept for Airborne Applications

Deployment of a satellite borne, steerable antenna array with higher directivity and gain in Low Earth Orbit makes sense to reduce ground station complexity and cost, while still maintaining a reasonable link budget. The implementation comprises a digitally beam steerable phased array antenna integrated with a complete system, comprising the antenna, hosting platform, ground station, and aircraft based satellite emulator to facilitate convenient aircraft based testing of the antenna array and ground-space communication link. This paper describes the design, development and initial successful interim testing of the various subsystems. A two element prototype used in this increases the signal-to-noise ratio (SNR) by 3 dB which is corresponding to more than 10 times better bit error rate (BER)