Predictive control using an FPGA with application to aircraft control

Alternative and more efficient computational methods can extend the applicability of MPC to systems with tight real-time requirements. This paper presents a “system-on-a-chip” MPC system, implemented on a field programmable gate array (FPGA), consisting of a sparse structure-exploiting primal dual interior point (PDIP) QP solver for MPC reference tracking and a fast gradient QP solver for steady-state target calculation. A parallel reduced precision iterative solver is used to accelerate the solution of the set of linear equations forming the computational bottleneck of the PDIP algorithm. A numerical study of the effect of reducing the number of iterations highlights the effectiveness of the approach. The system is demonstrated with an FPGA-inthe-loop testbench controlling a nonlinear simulation of a large airliner. This study considers many more manipulated inputs than any previous FPGA-based MPC implementation to date, yet the implementation comfortably fits into a mid-range FPGA, and the controller compares well in terms of solution quality and latency to state-of-the-art QP solvers running on a standard PC

Custom optimization algorithms for efficient hardware implementation

The focus is on real-time optimal decision making with application in advanced control systems. These computationally intensive schemes, which involve the repeated solution of (convex) optimization problems within a sampling interval, require more efficient computational methods than currently available for extending their application to highly dynamical systems and setups with resource-constrained embedded computing platforms. A range of techniques are proposed to exploit synergies between digital hardware, numerical analysis and algorithm design. These techniques build on top of parameterisable hardware code generation tools that generate VHDL code describing custom computing architectures for interior-point methods and a range of first-order constrained optimization methods. Since memory limitations are often important in embedded implementations we develop a custom storage scheme for KKT matrices arising in interior-point methods for control, which reduces memory requirements significantly and prevents I/O bandwidth limitations from affecting the performance in our implementations. To take advantage of the trend towards parallel computing architectures and to exploit the special characteristics of our custom architectures we propose several high-level parallel optimal control schemes that can reduce computation time. A novel optimization formulation was devised for reducing the computational effort in solving certain problems independent of the computing platform used. In order to be able to solve optimization problems in fixed-point arithmetic, which is significantly more resource-efficient than floating-point, tailored linear algebra algorithms were developed for solving the linear systems that form the computational bottleneck in many optimization methods. These methods come with guarantees for reliable operation. We also provide finite-precision error analysis for fixed-point implementations of first-order methods that can be used to minimize the use of resources while meeting accuracy specifications. The suggested techniques are demonstrated on several practical examples, including a hardware-in-the-loop setup for optimization-based control of a large airliner.Open Acces

Predictive control using an FPGA with application to aircraft control

Alternative and more efficient computational methods can extend the applicability of MPC to systems with tight real-time requirements. This paper presents a ``system-on-a-chip'' MPC system, implemented on a field programmable gate array (FPGA), consisting of a sparse structure-exploiting primal dual interior point (PDIP) QP solver for MPC reference tracking and a fast gradient QP solver for steady-state target calculation. A parallel reduced precision iterative solver is used to accelerate the solution of the set of linear equations forming the computational bottleneck of the PDIP algorithm. A numerical study of the effect of reducing the number of iterations highlights the effectiveness of the approach. The system is demonstrated with an FPGA-in-the-loop testbench controlling a nonlinear simulation of a large airliner. This study considers many more manipulated inputs than any previous FPGA-based MPC implementation to date, yet the implementation comfortably fits into a mid-range FPGA, and the controller compares well in terms of solution quality and latency to state-of-the-art QP solvers running on a standard PC.This work was supported by EPSRC (Grants EP/G030308/1, EP/G031576/1 and EP/I012036/1) and the EU FP7 Project EMBOCON grant agreement number FP7-ICT-2009-4 248940, as well as industrial support from Xilinx, the Mathworks, and the European Space Agency.This is the author's version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at: http://dx.doi.org/10.1109/TCST.2013.2271791. Copyright (c) 2014 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing [email protected]

Computer Architectures to Close the Loop in Real-time Optimization

© 2015 IEEE.Many modern control, automation, signal processing and machine learning applications rely on solving a sequence of optimization problems, which are updated with measurements of a real system that evolves in time. The solutions of each of these optimization problems are then used to make decisions, which may be followed by changing some parameters of the physical system, thereby resulting in a feedback loop between the computing and the physical system. Real-time optimization is not the same as fast optimization, due to the fact that the computation is affected by an uncertain system that evolves in time. The suitability of a design should therefore not be judged from the optimality of a single optimization problem, but based on the evolution of the entire cyber-physical system. The algorithms and hardware used for solving a single optimization problem in the office might therefore be far from ideal when solving a sequence of real-time optimization problems. Instead of there being a single, optimal design, one has to trade-off a number of objectives, including performance, robustness, energy usage, size and cost. We therefore provide here a tutorial introduction to some of the questions and implementation issues that arise in real-time optimization applications. We will concentrate on some of the decisions that have to be made when designing the computing architecture and algorithm and argue that the choice of one informs the other

Fixed-point implementation of a proximal Newton method for embedded model predictive control (I)

Extending the success of model predictive control (MPC) technologies in embedded applications heavily depends on the capability of improving quadratic programming (QP) solvers. Improvements can be done in two directions: better algorithms that reduce the number of arithmetic operations required to compute a solution, and more efficient architectures in terms of speed, power consumption, memory occupancy and cost. This paper proposes a fixed point implementation of a proximal Newton method to solve optimization problems arising in input-constrained MPC. The main advantages of the algorithm are its fast asymptotic convergence rate and its relatively low computational cost per iteration since it the solution of a small linear system is required. A detailed analysis on the effects of quantization errors is presented, showing the robustness of the algorithm with respect to finite-precision computations. A hardware implementation with specific optimizations to minimize computation times and memory footprint is also described, demonstrating the viability of low-cost, low-power controllers for high-bandwidth MPC applications. The algorithm is shown to be very effective for embedded MPC applications through a number of simulation experiments

A hierarchical time-splitting approach for solving finite-time optimal control problems

We present a hierarchical computation approach for solving finite-time optimal control problems using operator splitting methods. The first split is performed over the time index and leads to as many subproblems as the length of the prediction horizon. Each subproblem is solved in parallel and further split into three by separating the objective from the equality and inequality constraints respectively, such that an analytic solution can be achieved for each subproblem. The proposed solution approach leads to a nested decomposition scheme, which is highly parallelizable. We present a numerical comparison with standard state-of-the-art solvers, and provide analytic solutions to several elements of the algorithm, which enhances its applicability in fast large-scale applications

Embedded ADMM-based QP solver for MPC with polytopic constraints

We propose an algorithm for solving quadratic programming (QP) problems with inequality and equality constraints arising from linear MPC. The proposed algorithm is based on the ‘alternating direction method of multipliers’ (ADMM), with the introduction of slack variables. In comparison with algorithms available in the literature, our proposed algorithm can handle the so-called sparse MPC formulation with general inequality constraints. Moreover, our proposed algorithm is suitable for implementation on embedded platforms where computational resources are limited. In some cases, our algorithm is division-free when certain fixed matrices are computed offline. This enables our algorithm to be implemented in fixed-point arithmetic on a FPGA. In this paper, we also propose heuristic rules to select the step size of ADMM for a good convergence rate.This is the author accepted manuscript. The final version is available from IEEE via http://dx.doi.org/10.1109/ECC.2015.733106