Robust Automatic Speech recognition System Implemented in a Hybrid Design DSP-FPGA

The aim of this work is to reduce the burden task on the DSP processor by transferring a parallel computation part on a configurable circuits FPGA, in automatic speech recognition module design, signal pre-processing, feature selection and optimization, models construction and finally classification phase are necessary. LMS filter algorithm that contains more parallelism and more MACs (multiply and Accumulate) operations is implemented on FPGA Virtex 5 by Xilings, MFCCs features extraction and DTW ( dynamic time wrapping) method is used as a classifier. Major contribution of this work are hybrid solution DSP and FPGA in real time speech recognition system design, the optimization of number of MAC-core within the FPGA this result is obtained by sharing MAC resources between two operation phases: computation of output filter and updating LMS filter coefficients. The paper also provides a hardware solution of the filter with detailed description of asynchronous interface of FPGA circuit and TMS320C6713-EMIF component. The results of simulation shows an improvement in time computation and by optimizing the implementation on the FPGA a gain in space consumption is obtained

Sound Localization using VHDL

Sound localization based on listener's potential to address the location or source of a located sound in orientation and distance. Rather than detecting what has been spoken, the work concerns about the detection of where the sound comes from. Speech enhancement aims to improve speech quality by using various algorithms. The purpose of enhancement is to increase user-friendliness and overall excellence of degraded speech signal using audio signal filtering techniques. The better speech quality improves by sign-error LMS algorithm. FPGAs have become a competitive alternative for high performance DSP applications, previously dominated by general purpose DSP and ASIC devices. The FPGA is useful for many multimedia applications and functional systems. The FPGA can be programmed to perform any number of parallel paths

Adaptive multichannel control of time-varying broadband noise and vibrations

This paper presents results obtained from a number of applications in which a recent adaptive algorithm for broadband multichannel active noise control is used. The core of the algorithm uses the inverse of the minimum-phase part of the secondary path for improvement of the speed of convergence. A further improvement of the speed of convergence is obtained by using double control filters for elimination of adaptation loop delay. Regularization was found to be necessary for robust operation. The regularization technique which is used preserves the structure to eliminate the adaptation loop delay. Depending on the application at hand, a number of extensions are used for this algorithm. For an application with rapidly changing disturbance spectra, the core algorithm was extended with an iterative affine projection scheme, leading to improved convergence rates as compared to the standard nomalized lms update rules. In another application, in which the influence of the parametric uncertainties was critical, the core algorithm was extended with low authority control loops operating at high sample rates. In addition, results of other applications are given, such as control of acoustic energy density and control of time-varying periodic and non-periodic vibrations

Design of LMS algorithm for noise canceller based on FPGA

This paper presents the design of an adapting filtering method to remove the noise in the biomedical signal records. The major concern about analyze the presence of various artifacts in ECG records and modular artifacts in EEG records caused due to various noise factors. Here, we have proposed a design based on LMS (Least Mean Square) algorithm to remove the artifacts from biomedical signal using Verilog HDL based on been mapped on  commercially available FPGAs (Field Programmable Gate Arrays). In this design the LMS algorithm used as a noise canceller and the reference signal was adaptively filtered and subtracted from primary signal to obtain the estimated biomedical signal. The original biomedical signal can be reconstructed by passing the digital bit stream through a low pass filter. This design is suitable for its low power biomedical instrument design and it reduces the whole system cost. Keywords: LMS algorithm, noise canceller, Verilog HDL, artifacts, biomedical signal, Low power application

Rapidly converging multichannel controllers for broadband noise and vibrations

Applications are given of a preconditioned adaptive algorithm for broadband multichannel active noise control. Based on state-space descriptions of the relevant transfer functions, the algorithm uses the inverse of the minimum-phase part of the secondary path in order to improve the speed of convergence. A further improvement of the convergence rate is obtained by using double control filters for elimination of adaptation loop delay. Regularization was found to be essential for robust operation. The particular regularization technique preserves the structure to eliminate the adaptation loop delay. Depending on the application at hand, a number of extensions are used for this algorithm, such as for applications with rapidly changing disturbance spectra, applications with large parametric uncertainty, applications with control of time-varying acoustic energy density

VLSI Design and Implementation for Adaptive Filter using LMS Algorithm

Adaptive filters, as part of digital signal systems, have been widely used, as well as in applications such as adaptive noise cancellation, adaptive beam forming, channel equalization, and system identification. However, its implementation takes a great deal and becomes a very important field in digital system world. When FPGA (Field Programmable Logic Array) grows in area and provides a lot of facilities to the designers, it becomes an important competitor in the signal processing market. In general FIR structure has been used more successfully than IIR structure in adaptive filters. However, when the adaptive FIR filter was made this required appropriate algorithm to update the filter’s coefficients. The algorithm used to update the filter coefficient is the Least Mean Square (LMS) algorithm which is known for its simplification, low computational complexity, and better performance in different running environments. When compared to other algorithms used for implementing adaptive filters the LMS algorithm is seen to perform very well in terms of the number of iterations required for convergence. This phenomenon can be achieved by a sufficient choice of bit length to represent the filter’s coefficients. This paper presents a lowcost and high performance programmable digital finite impulse response (FIR) filter. It follows the adaptive algorithm used for the development of the system. The architecture employs the computation sharing algorithm to reduce the computation complexity

IMPLEMENTATION OF NOISE CANCELLATION WITH HARDWARE DESCRIPTION LANGUAGE

The objective of this project is to implement noise cancellation technique on an FPGA using Hardware Description Language. The performance of several adaptive algorithms is compared to determine the desirable algorithm used for adaptive noise cancellation system. The project will focus on the implementation of adaptive filter with least-meansquares (LMS) algorithm or normalized least-mean-squares (NLMS) algorithm to cancel acoustic noises. This noise consists of extraneous or unwanted waveforms that can interfere with communication. Due to the simplicity and effectiveness of adaptive noise cancellation technique, it is used to remove the noise component from the desired signal. The project is divided into four main parts: research, Matlab simulation, ModelSim simulation and hardware implementation. The project starts with research on several noise cancellation techniques, and then with Matlab code, Simulink and FDA tool, the adaptive noise cancellation system is designed with the implementation of the LMS algorithm, NLMS algorithm and recursive-least-square algorithm to remove the interference noise. By using the Matlab code and Simulink, the noise that interfered with a sinusoidal signal and a record of music can be removed. The original signal in turns can be retrieved from the noise corrupted signal by changing the coefficient of the filter. Since filter is the important component in adaptive filtering process, the filter is designed first before adding adaptive algorithm. A Finite Impulse Response (FIR) filter is designed and the desired result of functional simulation and timing simulation is obtained through ModelSim and Integrated Software Environment (ISE) software and FPGA implementation. Finally the adaptive algorithm is added to the filter, and implemented in the FPGA. The noise is greatly reduced in Matlab simulation, functional simulation and timing simulation. Hence the results of this project show that noise cancellation with adaptive filter is feasible

FPGA Implementation of Spectral Subtraction for In-Car Speech Enhancement and Recognition

The use of speech recognition in noisy environments requires the use of speech enhancement algorithms in order to improve recognition performance. Deploying these enhancement techniques requires significant engineering to ensure algorithms are realisable in electronic hardware. This paper describes the design decisions and process to port the popular spectral subtraction algorithm to a Virtex-4 field-programmable gate array (FPGA) device. Resource analysis shows the final design uses only 13% of the total available FPGA resources. Waveforms and spectrograms presented support the validity of the proposed FPGA design

Design of a reusable distributed arithmetic filter and its application to the affine projection algorithm

Digital signal processing (DSP) is widely used in many applications spanning the spectrum from audio processing to image and video processing to radar and sonar processing. At the core of digital signal processing applications is the digital filter which are implemented in two ways, using either finite impulse response (FIR) filters or infinite impulse response (IIR) filters. The primary difference between FIR and IIR is that for FIR filters, the output is dependent only on the inputs, while for IIR filters the output is dependent on the inputs and the previous outputs. FIR filters also do not sur from stability issues stemming from the feedback of the output to the input that aect IIR filters. In this thesis, an architecture for FIR filtering based on distributed arithmetic is presented. The proposed architecture has the ability to implement large FIR filters using minimal hardware and at the same time is able to complete the FIR filtering operation in minimal amount of time and delay when compared to typical FIR filter implementations. The proposed architecture is then used to implement the fast affine projection adaptive algorithm, an algorithm that is typically used with large filter sizes. The fast affine projection algorithm has a high computational burden that limits the throughput, which in turn restricts the number of applications. However, using the proposed FIR filtering architecture, the limitations on throughput are removed. The implementation of the fast affine projection adaptive algorithm using distributed arithmetic is unique to this thesis. The constructed adaptive filter shares all the benefits of the proposed FIR filter: low hardware requirements, high speed, and minimal delay.Ph.D.Committee Chair: Anderson, Dr. David V.; Committee Member: Hasler, Dr. Paul E.; Committee Member: Mooney, Dr. Vincent J.; Committee Member: Taylor, Dr. David G.; Committee Member: Vuduc, Dr. Richar

Realization of Delayed Least Mean Square Adaptive Algorithm using Verilog HDL for EEG Signals

An efficient architecture for the implementation of delayed least mean square (DLMS) adaptive filter is presented in this paper. It is shown that the proposed architectures reduces the register complexity and also supports the faster convergence. Compared to transpose form, the direct form LMS adaptive filter has fast convergence but both has most similar critical path. Further it is shown that in most of the practical cases, very small adaptation delay is sufficient enough to implement a direct-form LMS adaptive filter where in normal cases a very high sampling rate is required and also it shows that no pipelining approach is necessary. From the above discussed estimations three different architectures of LMS adaptive filter has been designed. They are, first design comprise of zero delays i.e., with no adaptation delays, second design comprises of only single delay i.e., with only one adaptation delay, and lastly the third design comprises of two adaptation delays. Among all the three designs zero adaptation delay structure gives efficient performance comparatively. Design with zero adaptation delay involves the minimum energy per sample (EPS) and also minimum area compared to other two designs. The aim of this thesis is to design an efficient filter structures to create a system-on-chip (SoC) solution by using an optimized code for solving various adaptive filtering problems in the system. In this thesis our main focus is on interference cancellation in electroencephalogram (EEG) applications by using the proposed filter structures. Modern field programmable gate arrays (FPGAs) have the resources that are required to design an effective adaptive filtering structures. The designs are evaluated in terms of design time, area and delays