9 research outputs found

    Multiple-Independent-Gate Field-Effect Transistors for High Computational Density and Low Power Consumption

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    Transistors are the fundamental elements in Integrated Circuits (IC). The development of transistors significantly improves the circuit performance. Numerous technology innovations have been adopted to maintain the continuous scaling down of transistors. With all these innovations and efforts, the transistor size is approaching the natural limitations of materials in the near future. The circuits are expected to compute in a more efficient way. From this perspective, new device concepts are desirable to exploit additional functionality. On the other hand, with the continuously increased device density on the chips, reducing the power consumption has become a key concern in IC design. To overcome the limitations of Complementary Metal-Oxide-Semiconductor (CMOS) technology in computing efficiency and power reduction, this thesis introduces the multiple- independent-gate Field-Effect Transistors (FETs) with silicon nanowires and FinFET structures. The device not only has the capability of polarity control, but also provides dual-threshold- voltage and steep-subthreshold-slope operations for power reduction in circuit design. By independently modulating the Schottky junctions between metallic source/drain and semiconductor channel, the dual-threshold-voltage characteristics with controllable polarity are achieved in a single device. This property is demonstrated in both experiments and simulations. Thanks to the compact implementation of logic functions, circuit-level benchmarking shows promising performance with a configurable dual-threshold-voltage physical design, which is suitable for low-power applications. This thesis also experimentally demonstrates the steep-subthreshold-slope operation in the multiple-independent-gate FETs. Based on a positive feedback induced by weak impact ionization, the measured characteristics of the device achieve a steep subthreshold slope of 6 mV/dec over 5 decades of current. High Ion/Ioff ratio and low leakage current are also simultaneously obtained with a good reliability. Based on a physical analysis of the device operation, feasible improvements are suggested to further enhance the performance. A physics-based surface potential and drain current model is also derived for the polarity-controllable Silicon Nanowire FETs (SiNWFETs). By solving the carrier transport at Schottky junctions and in the channel, the core model captures the operation with independent gate control. It can serve as the core framework for developing a complete compact model by integrating advanced physical effects. To summarize, multiple-independent-gate SiNWFETs and FinFETs are extensively studied in terms of fabrication, modeling, and simulation. The proposed device concept expands the family of polarity-controllable FETs. In addition to the enhanced logic functionality, the polarity-controllable SiNWFETs and FinFETs with the dual-threshold-voltage and steep-subthreshold-slope operation can be promising candidates for future IC design towards low-power applications

    Planar Electrostatically Doped Reconfigurable Schottky Barrier FDSOI Field-Effect Transistor Structures

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    In the last 50 years, our economy and society have obviously been influenced and shaped to a great extent by electronic devices. This substantial impact of electronics is the result of a continuous performance improvement based on the scaling, i.e. shrinking, of MOSFET devices in complementary integrated circuits, following Moore's law. As the MOSFET feature sizes are approaching atomistic dimensions, the scaling trend slowed down considerably and is even threatened for sub-10 nm technology nodes. Further, additional advancements are increasingly difficult to realize both from the technological and especially the economical perspective. Therefore, technologies that have the potential to supersede the CMOS technology in the future are the topic of intensive investigation by both researchers and the industry. An attractive solution is the leveraging of existing semiconductor technologies based on emerging research devices (ERD) offering novel characteristics, which enable new circuit architectures in future nanoscale logic circuits. A possible ERD contender are polarity controllable or reconfigurable MOSFET (RFET) concepts. Generally, RFET devices are able to switch between n- and p-type conduction by the application of an electrical signal. Therefore, RFET promise increased complex systems with a lower device count decreasing the costs per basic logic function based on their higher logic expressiveness. The focus of this work lies in the successful transfer of a predecessor silicon nanowire (NW) RFET technology into a planar RFET device, while simultaneously optimizing the resulting RFET for reconfigurable as well as conventional CMOS circuits. As for the predecessor NW RFET, the planar approach features a doping-less CMOS compatible fabrication process on a conventional SOI substrate and obtains its reconfigurability by electrostatic doping. The device can be regarded as a entanglement of two MOSFET in one structure, i.e. a depletion mode FET centered on top of a backside enhancement mode Schottky barrier FET (SBFET). The backside SBFET establishes the conductive channel consisting of the desired charge carrier type via an appropriate potential on its gate electrode. The topside FET controls the charge carrier flow between source and drain by locally depleting this channel given an opposite potential on its gate electrode with respect to the backside gate electrode. Two generations of devices have been successfully processed, while different gate electrode materials, i.e. nickel, aluminum and reactively sputtered tungsten-titanium-nitride, have been introduced to the device structure. As n- and p-type symmetry of the very same device is essential for RFET circuit design, tungsten-titanium-nitride is experimentally identified as a possible mid-gap metal gate electrode for RFET devices. Also, a Schottky barrier adjustment process for ideal n- and p-type symmetry based on silicide induced dopant segregation is experimentally demonstrated. Extensive electrical characterizations supported by calibrated TCAD simulations are presented, demonstrating experimental sub-threshold slopes of 65 mV/dec and on-to-off current ratios of over 9 decades. Based on TCAD simulations and supported by experimental results, the design space of the device concept is explored in order to gather predictive results for future scaled device optimization. Further, the high temperature (HT) performance is evaluated and compared to the predecessor NW RFET devices as well as to a state-of-the-art industrial high reliability HT MOSFET clearly illustrating the on par performance of the planar RFET concept with respect to off-state leakage current

    Design for Reliability and Low Power in Emerging Technologies

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    Die fortlaufende Verkleinerung von Transistor-StrukturgrĂ¶ĂŸen ist einer der wichtigsten Antreiber fĂŒr das Wachstum in der Halbleitertechnologiebranche. Seit Jahrzehnten erhöhen sich sowohl Integrationsdichte als auch KomplexitĂ€t von Schaltkreisen und zeigen damit einen fortlaufenden Trend, der sich ĂŒber alle modernen FertigungsgrĂ¶ĂŸen erstreckt. Bislang ging das Verkleinern von Transistoren mit einer Verringerung der Versorgungsspannung einher, was zu einer Reduktion der Leistungsaufnahme fĂŒhrte und damit eine gleichbleibenden Leistungsdichte sicherstellte. Doch mit dem Beginn von StrukturgrĂ¶ĂŸen im Nanometerbreich verlangsamte sich die fortlaufende Skalierung. Viele Schwierigkeiten, sowie das Erreichen von physikalischen Grenzen in der Fertigung und Nicht-IdealitĂ€ten beim Skalieren der Versorgungsspannung, fĂŒhrten zu einer Zunahme der Leistungsdichte und, damit einhergehend, zu erschwerten Problemen bei der Sicherstellung der ZuverlĂ€ssigkeit. Dazu zĂ€hlen, unter anderem, Alterungseffekte in Transistoren sowie ĂŒbermĂ€ĂŸige Hitzeentwicklung, nicht zuletzt durch stĂ€rkeres Auftreten von Selbsterhitzungseffekten innerhalb der Transistoren. Damit solche Probleme die ZuverlĂ€ssigkeit eines Schaltkreises nicht gefĂ€hrden, werden die internen Signallaufzeiten ĂŒblicherweise sehr pessimistisch kalkuliert. Durch den so entstandenen zeitlichen Sicherheitsabstand wird die korrekte FunktionalitĂ€t des Schaltkreises sichergestellt, allerdings auf Kosten der Performance. Alternativ kann die ZuverlĂ€ssigkeit des Schaltkreises auch durch andere Techniken erhöht werden, wie zum Beispiel durch Null-Temperatur-Koeffizienten oder Approximate Computing. Wenngleich diese Techniken einen Großteil des ĂŒblichen zeitlichen Sicherheitsabstandes einsparen können, bergen sie dennoch weitere Konsequenzen und Kompromisse. Bleibende Herausforderungen bei der Skalierung von CMOS Technologien fĂŒhren außerdem zu einem verstĂ€rkten Fokus auf vielversprechende Zukunftstechnologien. Ein Beispiel dafĂŒr ist der Negative Capacitance Field-Effect Transistor (NCFET), der eine beachtenswerte Leistungssteigerung gegenĂŒber herkömmlichen FinFET Transistoren aufweist und diese in Zukunft ersetzen könnte. Des Weiteren setzen Entwickler von Schaltkreisen vermehrt auf komplexe, parallele Strukturen statt auf höhere Taktfrequenzen. Diese komplexen Modelle benötigen moderne Power-Management Techniken in allen Aspekten des Designs. Mit dem Auftreten von neuartigen Transistortechnologien (wie zum Beispiel NCFET) mĂŒssen diese Power-Management Techniken neu bewertet werden, da sich AbhĂ€ngigkeiten und VerhĂ€ltnismĂ€ĂŸigkeiten Ă€ndern. Diese Arbeit prĂ€sentiert neue Herangehensweisen, sowohl zur Analyse als auch zur Modellierung der ZuverlĂ€ssigkeit von Schaltkreisen, um zuvor genannte Herausforderungen auf mehreren Designebenen anzugehen. Diese Herangehensweisen unterteilen sich in konventionelle Techniken ((a), (b), (c) und (d)) und unkonventionelle Techniken ((e) und (f)), wie folgt: (a)\textbf{(a)} Analyse von Leistungszunahmen in Zusammenhang mit der Maximierung von Leistungseffizienz beim Betrieb nahe der Transistor Schwellspannung, insbesondere am optimalen Leistungspunkt. Das genaue Ermitteln eines solchen optimalen Leistungspunkts ist eine besondere Herausforderung bei Multicore Designs, da dieser sich mit den jeweiligen Optimierungszielsetzungen und der Arbeitsbelastung verschiebt. (b)\textbf{(b)} Aufzeigen versteckter Interdependenzen zwischen Alterungseffekten bei Transistoren und Schwankungen in der Versorgungsspannung durch „IR-drops“. Eine neuartige Technik wird vorgestellt, die sowohl Über- als auch UnterschĂ€tzungen bei der Ermittlung des zeitlichen Sicherheitsabstands vermeidet und folglich den kleinsten, dennoch ausreichenden Sicherheitsabstand ermittelt. (c)\textbf{(c)} EindĂ€mmung von Alterungseffekten bei Transistoren durch „Graceful Approximation“, eine Technik zur Erhöhung der Taktfrequenz bei Bedarf. Der durch Alterungseffekte bedingte zeitlich Sicherheitsabstand wird durch Approximate Computing Techniken ersetzt. Des Weiteren wird Quantisierung verwendet um ausreichend Genauigkeit bei den Berechnungen zu gewĂ€hrleisten. (d)\textbf{(d)} EindĂ€mmung von temperaturabhĂ€ngigen Verschlechterungen der Signallaufzeit durch den Betrieb nahe des Null-Temperatur Koeffizienten (N-ZTC). Der Betrieb bei N-ZTC minimiert temperaturbedingte Abweichungen der Performance und der Leistungsaufnahme. Qualitative und quantitative Vergleiche gegenĂŒber dem traditionellen zeitlichen Sicherheitsabstand werden prĂ€sentiert. (e)\textbf{(e)} Modellierung von Power-Management Techniken fĂŒr NCFET-basierte Prozessoren. Die NCFET Technologie hat einzigartige Eigenschaften, durch die herkömmliche Verfahren zur Spannungs- und Frequenzskalierungen zur Laufzeit (DVS/DVFS) suboptimale Ergebnisse erzielen. Dies erfordert NCFET-spezifische Power-Management Techniken, die in dieser Arbeit vorgestellt werden. (f)\textbf{(f)} Vorstellung eines neuartigen heterogenen Multicore Designs in NCFET Technologie. Das Design beinhaltet identische Kerne; HeterogenitĂ€t entsteht durch die Anwendung der individuellen, optimalen Konfiguration der Kerne. Amdahls Gesetz wird erweitert, um neue system- und anwendungsspezifische Parameter abzudecken und die VorzĂŒge des neuen Designs aufzuzeigen. Die Auswertungen der vorgestellten Techniken werden mithilfe von Implementierungen und Simulationen auf Schaltkreisebene (gate-level) durchgefĂŒhrt. Des Weiteren werden Simulatoren auf Systemebene (system-level) verwendet, um Multicore Designs zu implementieren und zu simulieren. Zur Validierung und Bewertung der EffektivitĂ€t gegenĂŒber dem Stand der Technik werden analytische, gate-level und system-level Simulationen herangezogen, die sowohl synthetische als auch reale Anwendungen betrachten

    Miniaturized Transistors, Volume II

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    In this book, we aim to address the ever-advancing progress in microelectronic device scaling. Complementary Metal-Oxide-Semiconductor (CMOS) devices continue to endure miniaturization, irrespective of the seeming physical limitations, helped by advancing fabrication techniques. We observe that miniaturization does not always refer to the latest technology node for digital transistors. Rather, by applying novel materials and device geometries, a significant reduction in the size of microelectronic devices for a broad set of applications can be achieved. The achievements made in the scaling of devices for applications beyond digital logic (e.g., high power, optoelectronics, and sensors) are taking the forefront in microelectronic miniaturization. Furthermore, all these achievements are assisted by improvements in the simulation and modeling of the involved materials and device structures. In particular, process and device technology computer-aided design (TCAD) has become indispensable in the design cycle of novel devices and technologies. It is our sincere hope that the results provided in this Special Issue prove useful to scientists and engineers who find themselves at the forefront of this rapidly evolving and broadening field. Now, more than ever, it is essential to look for solutions to find the next disrupting technologies which will allow for transistor miniaturization well beyond silicon’s physical limits and the current state-of-the-art. This requires a broad attack, including studies of novel and innovative designs as well as emerging materials which are becoming more application-specific than ever before

    An Exploration of Applying Gate-Length-Biasing Techniques to Deeply-Scaled FinFETs Operating in Multiple Voltage Regimes

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    Silicon nanodevice qubits based on quantum dots and dopants

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    Quantum physics applied to computing is predicted to lead to revolutionary enhancements in computational speed and power. The interest in the implementation of an impurity spin based qubit in silicon for quantum computation is motivated by exceedingly long coherence times of the order of seconds, an advantage of silicon's low spin orbit coupling and its ability to be isotopically enriched to the nuclear spin zero form. In addition, the donor spin in silicon is tunable, its nuclear spin is available to be employed as a quantum memory, and there are major advantages to working with silicon in terms of infrastructure and scalability. In contrast, lithographically patterned artificial atoms called quantum dots have the complementary advantages of fast electrical operations and tunability. Here I present our attempts to develop a scalable quantum computation architecture in silicon, based on a coupled quantum dot and dopant system. I explore industry-compatible as well as industrial foundry-fabricated devices in silicon as hosts for few-electron quantum dots and utilise a high-sensitivity readout and charge sensing technique, gate-based radiofrequency reflectometry, for this purpose. I show few-electron quantum dot measurements in this device architecture, leading to a charge qubit with a novel multi-regime Landau-Zener interferometry signature, with possible applications for readout sensitivity. I also present spin-to-charge conversion measurements of a chalcogen donor atom in silicon. Lastly, I perform measurements on a foundry-fabricated silicon device showing a coupling between a donor atom and a quantum dot. I probe the relevant charge dynamics of the charge qubit, as well as observe Pauli spin blockade in the hybrid spin system, opening up the possibility to operate this coupled double quantum dot as a singlet-triplet qubit or to transfer a coherent spin state between the quantum dot and the donor electron and nucleus

    Electronic Nanodevices

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    The start of high-volume production of field-effect transistors with a feature size below 100 nm at the end of the 20th century signaled the transition from microelectronics to nanoelectronics. Since then, downscaling in the semiconductor industry has continued until the recent development of sub-10 nm technologies. The new phenomena and issues as well as the technological challenges of the fabrication and manipulation at the nanoscale have spurred an intense theoretical and experimental research activity. New device structures, operating principles, materials, and measurement techniques have emerged, and new approaches to electronic transport and device modeling have become necessary. Examples are the introduction of vertical MOSFETs in addition to the planar ones to enable the multi-gate approach as well as the development of new tunneling, high-electron mobility, and single-electron devices. The search for new materials such as nanowires, nanotubes, and 2D materials for the transistor channel, dielectrics, and interconnects has been part of the process. New electronic devices, often consisting of nanoscale heterojunctions, have been developed for light emission, transmission, and detection in optoelectronic and photonic systems, as well for new chemical, biological, and environmental sensors. This Special Issue focuses on the design, fabrication, modeling, and demonstration of nanodevices for electronic, optoelectronic, and sensing applications

    Feature Papers in Electronic Materials Section

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    This book entitled "Feature Papers in Electronic Materials Section" is a collection of selected papers recently published on the journal Materials, focusing on the latest advances in electronic materials and devices in different fields (e.g., power- and high-frequency electronics, optoelectronic devices, detectors, etc.). In the first part of the book, many articles are dedicated to wide band gap semiconductors (e.g., SiC, GaN, Ga2O3, diamond), focusing on the current relevant materials and devices technology issues. The second part of the book is a miscellaneous of other electronics materials for various applications, including two-dimensional materials for optoelectronic and high-frequency devices. Finally, some recent advances in materials and flexible sensors for bioelectronics and medical applications are presented at the end of the book
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