Assessing the role of mini-applications in predicting key performance characteristics of scientific and engineering applications

Computational science and engineering application programs are typically large, complex, and dynamic, and are often constrained by distribution limitations. As a means of making tractable rapid explorations of scientific and engineering application programs in the context of new, emerging, and future computing architectures, a suite of "miniapps" has been created to serve as proxies for full scale applications. Each miniapp is designed to represent a key performance characteristic that does or is expected to significantly impact the runtime performance of an application program. In this paper we introduce a methodology for assessing the ability of these miniapps to effectively represent these performance issues. We applied this methodology to three miniapps, examining the linkage between them and an application they are intended to represent. Herein we evaluate the fidelity of that linkage. This work represents the initial steps required to begin to answer the question, "Under what conditions does a miniapp represent a key performance characteristic in a full app?

Design of an Autonomous Platform for Search and Rescue UAV Networks

This project designed and implemented a platform for use in a system of unmanned aerial vehicles (UAVs) capable of human assisted-autonomous and fully autonomous flight for search and rescue applications to improve the speed, efficiency, and safety of search and rescue to benefit both the victims and the rescuers alike. To accomplish this, the platform was designed to be lightweight with long endurance, equipped with specialized search and rescue sensors, and utilizes the paparazzi autopilot system, which is an open source, Linux based autopilot package for flight stability and autonomous control

Reusable modelling and simulation of flexible manufacturing for next generation semiconductor manufacturing facilities

Automated material handling systems (AMHS) in 300 mm semiconductor manufacturing facilities may need to evolve faster than expected considering the high performance demands on these facilities. Reusable simulation models are needed to cope with the demands of this dynamic environment and to deliver answers to the industry much faster. One vision for intrabay AMHS is to link a small group of intrabay AMHS systems, within a full manufacturing facility, together using what is called a Merge/Diverge link. This promises better operational performance of the AMHS when compared to operating two dedicated AMHS systems, one for interbay transport and the other for intrabay handling. A generic tool for modelling and simulation of an intrabay AMHS (GTIA-M&S) is built, which utilises a library of different blocks representing the different components of any intrabay material handling system. GTIA-M&S provides a means for rapid building and analysis of an intrabay AMHS under different operating conditions. The ease of use of the tool means that inexpert users have the ability to generate good models. Models developed by the tool can be executed with the merge/diverge capability enabled or disabled to provide comparable solutions to production demands and to compare these two different configurations of intrabay AMHS using a single simulation model. Finally, results from simulation experiments on a model developed using the tool were very informative in that they include useful decision making data, which can now be used to further enhance and update the design and operational characteristics of the intrabay AMHS

Development of a seamlessly integrated factory planning software tool (prototype) to evaluate and optimize surface mount manufacturing lines

Thesis (M.S.)--Massachusetts Institute of Technology, Sloan School of Management, 1995.Includes bibliographical references (p. 182).by Vijay Mehra.M.S

SPICE²: A Spatial, Parallel Architecture for Accelerating the Spice Circuit Simulator

Spatial processing of sparse, irregular floating-point computation using a single FPGA enables up to an order of magnitude speedup (mean 2.8X speedup) over a conventional microprocessor for the SPICE circuit simulator. We deliver this speedup using a hybrid parallel architecture that spatially implements the heterogeneous forms of parallelism available in SPICE. We decompose SPICE into its three constituent phases: Model-Evaluation, Sparse Matrix-Solve, and Iteration Control and parallelize each phase independently. We exploit data-parallel device evaluations in the Model-Evaluation phase, sparse dataflow parallelism in the Sparse Matrix-Solve phase and compose the complete design in streaming fashion. We name our parallel architecture SPICE²: Spatial Processors Interconnected for Concurrent Execution for accelerating the SPICE circuit simulator. We program the parallel architecture with a high-level, domain-specific framework that identifies, exposes and exploits parallelism available in the SPICE circuit simulator. This design is optimized with an auto-tuner that can scale the design to use larger FPGA capacities without expert intervention and can even target other parallel architectures with the assistance of automated code-generation. This FPGA architecture is able to outperform conventional processors due to a combination of factors including high utilization of statically-scheduled resources, low-overhead dataflow scheduling of fine-grained tasks, and overlapped processing of the control algorithms. We demonstrate that we can independently accelerate Model-Evaluation by a mean factor of 6.5X(1.4--23X) across a range of non-linear device models and Matrix-Solve by 2.4X(0.6--13X) across various benchmark matrices while delivering a mean combined speedup of 2.8X(0.2--11X) for the two together when comparing a Xilinx Virtex-6 LX760 (40nm) with an Intel Core i7 965 (45nm). With our high-level framework, we can also accelerate Single-Precision Model-Evaluation on NVIDIA GPUs, ATI GPUs, IBM Cell, and Sun Niagara 2 architectures. We expect approaches based on exploiting spatial parallelism to become important as frequency scaling slows down and modern processing architectures turn to parallelism (\eg multi-core, GPUs) due to constraints of power consumption. This thesis shows how to express, exploit and optimize spatial parallelism for an important class of problems that are challenging to parallelize.</p

Digital signal processor fundamentals and system design

Digital Signal Processors (DSPs) have been used in accelerator systems for more than fifteen years and have largely contributed to the evolution towards digital technology of many accelerator systems, such as machine protection, diagnostics and control of beams, power supply and motors. This paper aims at familiarising the reader with DSP fundamentals, namely DSP characteristics and processing development. Several DSP examples are given, in particular on Texas Instruments DSPs, as they are used in the DSP laboratory companion of the lectures this paper is based upon. The typical system design flow is described; common difficulties, problems and choices faced by DSP developers are outlined; and hints are given on the best solution

Advanced Platform Systems Technology study. Volume 2: Trade study and technology selection

Three primary tasks were identified which include task 1-trade studies, task 2-trade study comparison and technology selection, and task 3-technology definition. Task 1 general objectives were to identify candidate technology trade areas, determine which areas have the highest potential payoff, define specific trades within the high payoff areas, and perform the trade studies. In order to satisfy these objectives, a structured, organized approach was employed. Candidate technology areas and specific trades were screened using consistent selection criteria and considering possible interrelationships. A data base comprising both manned and unmanned space platform documentation was used as a source of system and subsystem requirements. When requirements were not stated in the data base documentation, assumptions were made and recorded where necessary to characterize a particular spacecraft system. The requirements and assumptions were used together with the selection criteria to establish technology advancement goals and select trade studies. While both manned and unmanned platform data were used, the study was focused on the concept of an early manned space station

The NASA computer science research program plan

A taxonomy of computer science is included, one state of the art of each of the major computer science categories is summarized. A functional breakdown of NASA programs under Aeronautics R and D, space R and T, and institutional support is also included. These areas were assessed against the computer science categories. Concurrent processing, highly reliable computing, and information management are identified