155 research outputs found
An Experimental Microarchitecture for a Superconducting Quantum Processor
Quantum computers promise to solve certain problems that are intractable for
classical computers, such as factoring large numbers and simulating quantum
systems. To date, research in quantum computer engineering has focused
primarily at opposite ends of the required system stack: devising high-level
programming languages and compilers to describe and optimize quantum
algorithms, and building reliable low-level quantum hardware. Relatively little
attention has been given to using the compiler output to fully control the
operations on experimental quantum processors. Bridging this gap, we propose
and build a prototype of a flexible control microarchitecture supporting
quantum-classical mixed code for a superconducting quantum processor. The
microarchitecture is based on three core elements: (i) a codeword-based event
control scheme, (ii) queue-based precise event timing control, and (iii) a
flexible multilevel instruction decoding mechanism for control. We design a set
of quantum microinstructions that allows flexible control of quantum operations
with precise timing. We demonstrate the microarchitecture and microinstruction
set by performing a standard gate-characterization experiment on a transmon
qubit.Comment: 13 pages including reference. 9 figure
Full-Stack, Real-System Quantum Computer Studies: Architectural Comparisons and Design Insights
In recent years, Quantum Computing (QC) has progressed to the point where
small working prototypes are available for use. Termed Noisy Intermediate-Scale
Quantum (NISQ) computers, these prototypes are too small for large benchmarks
or even for Quantum Error Correction, but they do have sufficient resources to
run small benchmarks, particularly if compiled with optimizations to make use
of scarce qubits and limited operation counts and coherence times. QC has not
yet, however, settled on a particular preferred device implementation
technology, and indeed different NISQ prototypes implement qubits with very
different physical approaches and therefore widely-varying device and machine
characteristics.
Our work performs a full-stack, benchmark-driven hardware-software analysis
of QC systems. We evaluate QC architectural possibilities, software-visible
gates, and software optimizations to tackle fundamental design questions about
gate set choices, communication topology, the factors affecting benchmark
performance and compiler optimizations. In order to answer key cross-technology
and cross-platform design questions, our work has built the first top-to-bottom
toolflow to target different qubit device technologies, including
superconducting and trapped ion qubits which are the current QC front-runners.
We use our toolflow, TriQ, to conduct {\em real-system} measurements on 7
running QC prototypes from 3 different groups, IBM, Rigetti, and University of
Maryland. From these real-system experiences at QC's hardware-software
interface, we make observations about native and software-visible gates for
different QC technologies, communication topologies, and the value of
noise-aware compilation even on lower-noise platforms. This is the largest
cross-platform real-system QC study performed thus far; its results have the
potential to inform both QC device and compiler design going forward.Comment: Preprint of a publication in ISCA 201
Optimized Compilation of Aggregated Instructions for Realistic Quantum Computers
Recent developments in engineering and algorithms have made real-world
applications in quantum computing possible in the near future. Existing quantum
programming languages and compilers use a quantum assembly language composed of
1- and 2-qubit (quantum bit) gates. Quantum compiler frameworks translate this
quantum assembly to electric signals (called control pulses) that implement the
specified computation on specific physical devices. However, there is a
mismatch between the operations defined by the 1- and 2-qubit logical ISA and
their underlying physical implementation, so the current practice of directly
translating logical instructions into control pulses results in inefficient,
high-latency programs. To address this inefficiency, we propose a universal
quantum compilation methodology that aggregates multiple logical operations
into larger units that manipulate up to 10 qubits at a time. Our methodology
then optimizes these aggregates by (1) finding commutative intermediate
operations that result in more efficient schedules and (2) creating custom
control pulses optimized for the aggregate (instead of individual 1- and
2-qubit operations). Compared to the standard gate-based compilation, the
proposed approach realizes a deeper vertical integration of high-level quantum
software and low-level, physical quantum hardware. We evaluate our approach on
important near-term quantum applications on simulations of superconducting
quantum architectures. Our proposed approach provides a mean speedup of
, with a maximum of . Because latency directly affects the
feasibility of quantum computation, our results not only improve performance
but also have the potential to enable quantum computation sooner than otherwise
possible.Comment: 13 pages, to apper in ASPLO
Optimizing Quantum Programs against Decoherence: Delaying Qubits into Quantum Superposition
Quantum computing technology has reached a second renaissance in the last
decade. However, in the NISQ era pointed out by John Preskill in 2018, quantum
noise and decoherence, which affect the accuracy and execution effect of
quantum programs, cannot be ignored and corrected by the near future NISQ
computers. In order to let users more easily write quantum programs, the
compiler and runtime system should consider underlying quantum hardware
features such as decoherence. To address the challenges posed by decoherence,
in this paper, we propose and prototype QLifeReducer to minimize the qubit
lifetime in the input OpenQASM program by delaying qubits into quantum
superposition. QLifeReducer includes three core modules, i.e.,the parser,
parallelism analyzer and transformer. It introduces the layered bundle format
to express the quantum program, where a set of parallelizable quantum
operations is packaged into a bundle. We evaluate quantum programs before and
after transformed by QLifeReducer on both real IBM Q 5 Tenerife and the
self-developed simulator. The experimental results show that QLifeReducer
reduces the error rate of a quantum program when executed on IBMQ 5 Tenerife by
11%; and can reduce the longest qubit lifetime as well as average qubit
lifetime by more than 20% on most quantum workloads.Comment: To appear in TASE2019 - the 13th International Symposium on
Theoretical Aspects of Software Engineering (submitted on Jan 25, 2019, and
this is camera-ready version
HiSEP-Q: A Highly Scalable and Efficient Quantum Control Processor for Superconducting Qubits
Quantum computing promises an effective way to solve targeted problems that
are classically intractable. Among them, quantum computers built with
superconducting qubits are considered one of the most advanced technologies,
but they suffer from short coherence times. This can get exaggerated when they
are controlled directly by general-purpose host machines, which leads to the
loss of quantum information. To mitigate this, we need quantum control
processors (QCPs) positioned between quantum processing units and host machines
to reduce latencies. However, existing QCPs are built on top of designs with no
or inefficient scalability, requiring a large number of instructions when
scaling to more qubits. In addition, interactions between current QCPs and host
machines require frequent data transmissions and offline computations to obtain
final results, which limits the performance of quantum computers.
In this paper, we propose a QCP called HiSEP-Q featuring a novel quantum
instruction set architecture (QISA) and its microarchitecture implementation.
For efficient control, we utilize mixed-type addressing modes and mixed-length
instructions in HiSEP-Q, which provides an efficient way to concurrently
address more than 100 qubits. Further, for efficient read-out and analysis, we
develop a novel onboard accumulation and sorting unit, which eliminates the
data transmission of raw data between the QCPs and host machines and enables
real-time result processing. Compared to the state-of-the-art, our proposed
QISA achieves at least 62% and 28% improvements in encoding efficiency with
real and synthetic quantum circuits, respectively. We also validate the
microarchitecture on a field-programmable gate array, which exhibits low power
and resource consumption. Both hardware and ISA evaluations demonstrate that
HiSEP-Q features high scalability and efficiency toward the number of
controlled qubits.Comment: The paper is accepted by the 41st IEEE International Conference on
Computer Design (ICCD), 202
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