An experimental investigation of MOSFET intrisic body diode performance

In order to enable evaluation of power loss during both forward and reverse conduction of intrinsic body diodes in power MOSFETs, an experimental series is performed to derive a set of expressions to approximate performance. A set of relevant performance metrics are selected, and then tested over a range of devices. Any correlation between these metrics and properties of these devices commonly provided by device manufacturers are investigated and quantified. A set of empirical expressions are derived from the closest correlations found, that therefore enable an estimation of performance of the body diode without any prior testing, with a predicted margin of error

Design and Assessment of a Grid Connected Industrial Full-SiC Converter for 690 V Grids

Die Bedeutung von Leistungshalbleitern mit großem Bandabstand (Wide Band Gap, WBG) nahm in den letzten drei Jahrzehnten kontinuierlich zu. Diese Bauelemente haben das Potenzial, Silizium (Si) - Bauelemente in bestimmten Anwendungen sowie Leistungs- und Frequenzbereichen zu ersetzen. Siliziumkarbid (SiC)-Leistungshalbleiter sind die gegenwärtig am Weitesten entwickelten WBG-Leistungshalbleiter. Dank besonderer Materialeigenschaften zeichnen sich SiC-Leistungshalbleiter im Vergleich zu Si-Bauelementen durch einen geringeren spezifischen Widerstand, eine höhere Schaltgeschwindigkeit, geringere schaltverluste sowie eine höhere maximale Sperrschichttemperatur aus. Die deutlich erhöhten Herstellungskosten limitieren den Einsatz von SiC-Leistungshalbleitern auf Anwendungen, in denen die Vorteile dieser Bauelemente die höheren Kosten überkompensieren und Systemvorteile ermöglichen. Heute werden SiC-Leistungshalbleiter z.B. in Solarwechselrichtern oder in Elektrofahrzeugen verwendet. Für Stromrichter industrieller elektrischer Antriebe ist die Kosten-Nutzen-Bilanz des Einsatzes von SiC-Leistungshalbleitern gegenwärtig nicht bekannt. Diese Fragestellung motiviert diese Arbeit. Die Auslegung sowie die daraus resultierenden Vor- und Nachteile eines Stromrichters mit SiC-Leistungshalbleitern für elektrische Industrieantriebe ist der Untersuchungsgegenstand dieser Arbeit. Zu diesem Zweck wurde unter Einhaltung industrieller Auslegungskriterien ein 240 kVA SiC-basierter Stromrichterdemonstrator als aktiver Gleichrichter am dreiphasigen 690 V Niederspannungsnetz untersucht. Auf der Basis einer Stromrichterauslegung für SiC- und Si-Leistungshalbleiter wurde ein theoretischer Vergleich von Kosten, Effizienz, Größe und Gewicht durchgeführt. Die Arbeit stellt zunächst den Stand der Technik für SiC-Leistungshalbleiter dar. Anschließend wird ein geeignetes SiC-MOSFET Module für den industriellen Stromrichter ausgewählt und bezüglich des Schaltverhaltens sowie der Parallelschaltung charakterisiert. Der Auslegung des Stromrichterleistungsteils liegen industrielle Anforderungen zu Grunde. Ein realisierter Demonstrator für einen netzseitigen Stromrichter (Active Front End) ist durch eine symmetrische Parallelschaltung von zwei SiC-Modulen, geeignete Ansteuerschaltungen (Gate Drive Units), eine niedrige Streuinduktivität im Kommutierungskreis sowie ein LCL-Filter mit Standard-Kernmaterialien gekennzeichnet. Der Stromrichtervergleich zeigt, dass der betrachtete Stromrichter mit SiC-Leistungshalbleitern im gesamten Betriebsbereich geringere Verluste verursacht als ein vergleichbarer Stromrichter mit Si-Leistungshalbleitern. Der SiC - basierte Stromichter ermöglicht auch eine deutliche Gewichtsreduktion bei ca. 89% der Systemkosten. Somit stellen SiC-Leistungshalbleiter eine attraktive technische Lösung für die untersuchte Anwendung eines aktiven Gleichrichters für industrielle elektrische Antriebe dar.Wide bandgap (WBG) power semiconductors have drawn steadily increasing interest in power electronics in the last three decades. These devices have shown the potential of replacing silicon as the default semiconductor solution for several applications in determined power and frequency ranges. Among them the most mature WBG semiconductor material is silicon carbide (SiC), which presents several characteristics at the crystal level that translate in the potential of presenting lower resistivity, be able to switch faster with lower switching loss, and present both higher characteristics to tolerate and dissipate heat when com pared with silicon. However, the same characteristics that make it great also present a different set of drawbacks to be considered, which aligned with its increased cost make it challenging to assess if its advantages are justified for a particular application. Applications that highly value efficiency and/or power density are the most benefited, and converter solutions featuring the technology have already breached into these application markets. However in other applica tions, the line from which silicon carbide starts making sense in the cost/benefits/drawbacks balance is not clear. This is typically the case of industrial applications, which were the main focus and motivation of this work. Hence, in this work the main goal has been to determine the basic characteristics, advantages and limitations that SiC technology designs for industrial low voltage high power grid connected converters present. To that end, a 690 V, 240 kVA SiC-based grid-tied converter demonstrator following industrial design criteria has been developed. Then, based on this design procedure a theoretical comparison between a 690 V, 190 kVA SiC-based converter against a silicon-based converter designed for the same power output has been performed to compare them regarding cost, efficiency, size and weight. This work also comprises a thorough revision of the state of art of SiC devices, which led to the selection of the switching device. Additionally, a characterization of both single and parallel-connected operation of the semiconductor modules was performed, to determine the module characteristics and its suitability to build the SiC converter demonstrator. Results show that the converter demonstrator operates as designed, proving that is possible with the corresponding precautions to achieve: a low inductive power loop, balanced parallel connection of SiC modules, adequate driving circuits for the parallel-connected modules and an adequate filtering solution in compliance with grid-codes based on standard core materials for the selected switching frequency. Finally, the theoretical comparison between the two designed power converters shows that, attained to the conditions of the comparison, the SiC converter solution presents efficiency gains over the whole operating range, while presenting substantial weight savings at 89% of the costs of the Si-IGBT design, presenting itself as the cost-effective solution for the presented application requirements under the given design constraints

Two-Dimensional Analytical Modeling of Tunnel-FETs

Basat en un mecanisme de transport de corrent de banda a banda, el túnel-FET és capaç de superar la limitació de pendent sub-llindar física del MOSFET de 60 mV /dec. Per tant, s'ha convertit en un dels dispositius més prometedors per ser el successor del MOSFET clàssic en els últims anys. Aquesta tesi descriu tots els passos necessaris per modelar analíticament un Túnel-FET de doble porta. El model inclou una solució electrostàtica de dues dimensions en totes les regions del dispositiu, el que permet fins i tot simulacions hetero-unió del dispositiu. Per a un comportament més realista del dispositiu, cal tenir en compte el rendiment del dispositiu que limita els perfils de dopatge de forma Gaussiana en les unions del canal. Les expressions per a les probabilitats de túnel de banda a banda i les de Trap-Assisted-Tunneling (TAT) són executades per un enfocament WKB quasi bidimensional. El corrent del dispositiu es calcula mitjançant la teoria de transmissió de Landauer. El model és vàlid per a dispositius de canal curt i les estàncies estan ben comparades amb les dades de simulació TCAD Sentaurus i amb les medicions proporcionades. S'introdueix un modelo general per les flactuacions del dopant aleatoria, que prediu les influencies característiques del dispositiu en el corrent de sortida i el voltatge llindar. El model s'aplica al MOSFET, així com a dispositius TFET.Basado en un mecanismo de transporte de corriente banda a banda, el Tunnel-FET es capaz de superar la limitación de pendiente sub-umbral física del MOSFET de 60 mV/dec. Por lo tanto, esto lo convierte en uno de los dispositivos más prometedores para ser el sucesor del MOSFET clásico en los últimos años. Esta tesis describe todos los pasos necesarios para modelar analíticamente un Tunnel-FET de doble puerta. El modelo incluye una solución electrostática bidimensional en todas las regiones del dispositivo, lo que permite incluso simulaciones de hetero-unión del dispositivo. Para un comportamiento más realista del dispositivo se tiene en cuenta el rendimiento del dispositivo que limita los perfiles de dopaje de forma Gaussiana en las uniones del canal. Las expresiones para las probabilidades de túnel de banda a banda y de Trap-Assisted-Tunneling (TAT) se implementan mediante un enfoque de WKB cuasi bidimensional. La corriente del dispositivo se calcula mediante la teoría de transmisión de Landauer. El modelo es válido para dispositivos de canal corto y las estancias están bien comparadas con los datos de simulación TCAD Sentaurus y con las mediciones proporcionadas. Se introduce un modelo general para las fluctuaciones del dopado aleatorio, que predice las influencias características del dispositivo en la corriente de salida y el voltaje umbral. El modelo se aplica al MOSFET, así como a los dispositivos TFET.Based on a band-to-band current transport mechanism, the Tunnel-FET is able to overcome the physical subthreshold slope limitation of the MOSFET of 60 mV/dec. Therefore, it has become one of the most promising devices to be the successor of the classical MOSFET in the last few years. This thesis describes all necessary steps to analytically model a double-gate Tunnel-FET. The model includes a two-dimensional electrostatic solution in all device regions, which enables even hetero-junction device simulations. Device performance limiting Gaussian-shaped doping profiles at the channel junctions are taken into account for a realistic device behavior. Expressions for the band-to-band and trap-assisted-tunneling probabilities are implemented by a quasi two-dimensional WKB approach. The device current is calculated based on Landauer's transmission theory. The model is valid for short-channel devices and stays is good agreement with the TCAD Sentaurus simulation data and with the provided measurements. A general model for random-dopant-fluctuations is introduced, which predicts characteristic device influences on the output current and threshold voltage. The model is applied to MOSFET, as well as TFET devices

Strained Si heterojunction bioploar transistors

This dissertation addresses the world’s first demonstration of strained Si Heterojunction Bipolar Transistors (sSi HBTs). The conventional SiGe Heterojunction Bipolar Transistor (SiGe HBT), which was introduced as a commercial product in 1999 (after its first demonstration in 1988), has become an established device for high-speed applications. This is due to its excellent RF performance and compatibility with CMOS processing. It has enabled silicon-based technology to penetrate the rapidly growing market for wide bandwidth and wireless telecommunications once reserved for more expensive III–V technologies. SiGe HBTs is realised by the pseudomorphic growth of SiGe on a Si substrate, which allows engineering of the base region to improve performance. In this way the base has a smaller energy band gap than the emitter, which increases the gain. The energy band gap of SiGe reduces with increasing Ge composition, but the maximum Ge composition is limited by the amount of strain that can be accommodated within a given base layer thickness. Therefore, a new innovation is necessary to overcome this limitation and meet the continuous demand for high speed devices. Growing the SiGe base layer over a relaxed SiGe layer (Strain Relaxed Buffer) can increase the amount of Ge that can be incorporated in the base, hence, increasing the device performance. In this thesis, experimental data is presented to demonstrate the realisation of sSi HBTs. The performance of this novel device has been also investigated and explained using TCAD tool.EThOS - Electronic Theses Online ServiceEngineering and Physical Sciences Research CouncilGBUnited Kingdo

Development of high performance readout ASICs for silicon photomultipliers (SiPMs)

Silicon Photomultipliers (SiPMs) are novel kind of solid state photon detectors with ex- tremely high photon detection resolution. They are composed of hundreds or thousands of avalanche photon diode pixels connected in parallel. These avalanche photon diodes are operated in Geiger Mode. SiPMs have the same magnitude of multiplication gain compared to the conventional photomultipliers (PMTs). Moreover, they have a lot of advantages such as compactness, relatively low bias voltage and magnetic field immunity etc. Special readout electronics are required to preserve the high performance of the detector. KLauS and STiC are two CMOS ASIC chips designed in particular for SiPMs. KLauS is used for SiPM charge readout applications. Since SiPMs have a much larger detector capacitance compared to other solid state photon detectors such as PIN diodes and APDs, a few special techniques are used inside the chip to make sure a descent signal to noise ratio for pixel charge signal can be obtained. STiC is a chip dedicated to SiPM time-of-flight applications. High bandwidth and low jitter design schemes are mandatory for such applications where time jitter less than tens of picosends is required. Design schemes and error analysis as well as measurement results are presented in the thesis

Graphene field effect transistor based pressure sensors for tactile sensing applications

The development of electronic skin emulating human skin's functionality is a growing area of interest due to its prospect in autonomous and interactive robots, prosthesis and wearable health monitoring devices. In an effort to mimic human skin a number of sensors for the detection of various stimuli have been developed including pressure, strain and thermal sensors. Amongst them, a significant effort has been focused on the development of novel pressure sensors due to their potential in the aforementioned applications. A number of strategies have been adopted for the development of pressure sensors and in particular, there has been a growing interest in the development of field effect transistor (FET) based pressure sensors. This is due to the capability to develop large area high spatial resolution active matrix pressure sensor array. In recent times, there has been a growing demand for the development of flexible pressure sensors due to emerging applications such as smart prosthesis, interactive robots, and wearable electronics. The use of conventional material like Si for flexible electronic applications are limited owing to their rigid and brittle nature. This has led to the investigation of various novel materials like organic semiconductors, carbon nanotube, inorganic semiconductor nanowires, and graphene. Amongst them, graphene is an attractive choice owing to its intrinsic material properties such as its electronic and mechanical properties. Further, the complementary metal oxide semiconductor (CMOS) compatibility and ability to grow high-quality graphene over a large area, and its low optical absorption are some of the other attractive features for the development of large area transparent electronic applications. The high mobility of graphene would enable the development of low voltage devices attractive for flexible electronics applications. This thesis presents work on the development of graphene field effect transistor (GFET) based pressure sensors for tactile sensing applications. The developed sensor comprises of two main components: a top-gate GFET and a piezoelectric transducer layer. A commercially available chemical vapour deposition grown monolayer graphene on Cu foil (from Graphenea) was used as the channel material of the transistor. A high-k Al2O3 deposited by atomic layer deposition technique was employed as the top-gate dielectric. In particular, care was taken to ensure a low temperature CMOS compatible process was adopted for the development of GFET. This ensured that the developed fabrication process could be transferred directly for the development of flexible devices. The development of the transfer process, the impact of different polymers (used as supporting layer during the transfer process) on graphene and the optimisation of dielectric deposition process are discussed in the thesis. The piezoelectric transducer layer is another vital component of the developed pressure sensor. In this respect, two piezoelectric materials, lead zirconate titanate (PZT) and aluminium nitride (AlN), have been investigated as the transducer layer. The pressure sensors were characterised with the piezoelectric transducer layer in an extended-gate configuration with GFET. PZT based pressure sensors exhibited a pressure sensitivity of 4.55E-3/kPa for a pressure range between 0 - 94.18 kPa. Though PZT is a better piezoelectric material than AlN, CMOS process incompatibility, non-biocompatibility and high processing temperature often associated with PZT limit its use in the development of flexible electronics especially for wearable applications. Therefore, AlN deposited by low temperature radio frequency magnetron sputtering has been explored as an alternate piezoelectric transducer layer for pressure sensing applications. The use of AlN also evades the need for the high voltage poling process often employed to enhance the piezoelectric property of the material. The AlN deposited via an optimised RF sputtering process reported in the thesis resulted in film with a piezoelectric constant of 5.9 pC/N. Similar to PZT , AlN was also characterised in an extended gate configuration and exhibited a sensitivity of 7.18 E-3 /kPa for a pressure range of 0-9.74 kPa. In an attempt to improve the spatial sensor resolution of sensor and to improve the signal to noise ratio a piezoelectric layer integrated within the top gate dielectric stack was investigated. In this regard,a flexible GFET with a piezoelectric layer integrated with the top-gate dielectric film was developed. The top gate dielectric stack comprise a 15 nm Al2O3(deposited by ALD)/ 90 nm AlN (deposited by RF sputtering). The developed device exhibited typical GFET electrical characteristics. The electron and hole mobility of the developed devices were 1612 cm2/V.s and 1568 cm2/V.s respectively. In addition, the device also displayed a stable electrical response under mechanical bending condition, thereby demonstrating its potential in the development of flexible electronics

Belle II Technical Design Report

The Belle detector at the KEKB electron-positron collider has collected almost 1 billion Y(4S) events in its decade of operation. Super-KEKB, an upgrade of KEKB is under construction, to increase the luminosity by two orders of magnitude during a three-year shutdown, with an ultimate goal of 8E35 /cm^2 /s luminosity. To exploit the increased luminosity, an upgrade of the Belle detector has been proposed. A new international collaboration Belle-II, is being formed. The Technical Design Report presents physics motivation, basic methods of the accelerator upgrade, as well as key improvements of the detector.Comment: Edited by: Z. Dole\v{z}al and S. Un