2 research outputs found
A novel datatype architecture support for programming languages
In programmers point of view, Datatypes in programming language level have a
simple description but inside hardware, huge machine codes are responsible to
describe type features. Datatype architecture design is a novel approach to
match programming features along with hardware design. In this paper a novel
Data type-Based Code Reducer (TYPELINE) architecture is proposed and
implemented according to significant data types (SDT) of programming languages.
TYPELINE uses TEUs for processing various SDT operations. This architecture
design leads to reducing the number of machine codes, and increases execution
speed, and also improves some parallelism level. This is because this
architecture supports some operation for the execution of Abstract Data Types
in parallel. Also it ensures to maintain data type features and entire
application level specifications using the proposed type conversion unit. This
framework includes compiler level identifying execution modes and memory
management unit for decreasing object read/write in heap memory by ISA support.
This energy-efficient architecture is completely compatible with object
oriented programming languages and in combination mode it can process complex
C++ data structures with respect to parallel TYPELINE architecture support.Comment: This paper is accepted and published in International journal of
Programming Languages and application
An Evaluation of Selective Depipelining for FPGA-based Energy-Reducing Irregular Code Coprocessors
Abstract — As the complexity of FPGA-based systems scales, the importance of efficiently handling irregular code increases. Recent work has proposed Irregular Code Energy Reducers (ICERs), a high-level synthesis approach for FPGAs that offers significant energy reduction for irregular code compared to a soft core processor. ICERs target the hot-spots of programs, and are seamlessly connected via a shared L1 cache with a soft processor that executes the cold code. This paper evaluates the application of the selective depipelining (SDP) technique to ICERs, which greatly reduces both the execution time and energy of irregular computations. SDP enables irregular computations to be expressed as large, fast, low-power combinational blocks. SDP maintains high memory bandwidth by scheduling the many potentially dependent memory operations within these blocks onto a high-frequency, highly-multiplexed coherent memory while scheduling combinational operations at a much lower frequency. SDP is a key enabler for improving the execution properties of irregular computations that are difficult to parallelize. We show that applying SDP to ICERs reduces energy-delay by 2.62 × relative to ICERs. ICERs with SDP are up to 2.38 × faster than a soft core processor and reduce energy consumption by up to 15.83 × for a variety of irregular applications. I