Compiling Esterel into Static Discrete-Event Code

Executing concurrent specifications on sequential hardware is important for both simulation of systems that are eventually implemented on concurrent hardware and for those most conveniently described as a set of concurrent processes. As with most forms of simulation, this is easy to do correctly but difficult to do efficiently. Solutions such as preemptive operating systems and discrete-event simulators present significant overhead. In this paper, we present a technique for compiling the concurrent language Esterel into very efficient C code. Our technique minimizes runtime overhead by making most scheduling decisions at compile time and using a very simple linked-list-based event queue at runtime. While these techniques work particularly well for Esterel with its high-level concurrent semantics, the same technique could also be applied to efficiently execute other concurrent specifications

A Concurrent Reactive Esterel Processor based on Multi-Threading

The synchronous language Esterel is well-suited for programming control-dominated reactive systems at the system level. It provides non-traditional control structures, in particular concurrency and various forms of preemption, which allow to concisely express reactive behavior. As these control structures cannot be mapped easily onto traditional, sequential processors, an alternative approach that has emerged recently makes use of special-purpose reactive processors. However, the designs proposed so far have limitations regarding completeness of the language support, and did not really take advantage of compile-time knowledge to optimize resource usage. This paper presents a reactive processor, the Kiel Esterel Processor 3a (KEP3a), and its compiler. The KEP3a improves on earlier designs in several areas; most notable are the support for exception handling and the provision of context-dependent preemption handling instructions. The KEP3a compiler presented here is to our knowledge the first for multi-threaded reactive processors. The translation of Esterel's preemption constructs onto KEP3a assembler is straightforward; however, a challenge is the correct and efficient representation of Esterel's concurrency. The compiler generates code that respects data and control dependencies using the KEP3a priority-based scheduling mechanism. We present a priority assignment approach that makes use of a novel concurrent control flow graph and has a complexity that in practice tends to be linear in the size of the program. Unlike earlier Esterel compilation schemes, this approach avoids unnecessary context switches by considering each thread's actual execution state at run time. Furthermore, it avoids code replication present in other approaches

Removing Cycles in Esterel Programs

Programs written in the synchronous programming language Esterel may contain statically cyclic dependencies of signals, which inhibits the application of certain compilation approaches that rely on static scheduling. This talk proposes an algorithm which, given a constructive synchronous program, performs a semantics-preserving source-level code transformation that removes cyclic signal dependencies. The transformation exploits the monotonicity of constructive programs, and is illustrated in the context of Esterel, but should be applicable to other synchronous languages as well

A Concurrent Reactive Esterel Processor Based on Multi-Threading

Esterel is a concurrent synchronous language for developing reactive systems. Classically, Esterel programs are either compiled into software, such as a C program that is then executed on a standard microprocessor, or into hardware. An alternative approach, which tries to combine the efficiency of a software solution with an efficiency close to a hardware solution, is the reactive processing approach, where the Esterel program is executed on a specialized processor. A principal difficulty when compiling onto a reactive processor is the faithful, efficient implementation of concurrency. One approach for implementing concurrency is multiprocessing, where sequential reactive processors are replicated and tightly synchronized to achieve concurrency. This allows concurrency at the top level; however, it is not obvious how this approach supports the arbitrary nesting of preemption and concurrency that is permitted in Esterel. This paper presents a novel reactive processor architecture, the Multi-threaded Esterel Processor (MEP), which overcomes this limitation and also scales well to large degrees of concurrency. Rather than replicating sequential processors, the MEP combines a single main processing element with independent control units that implement the concurrency and preemption operators and that allow the arbitrary combination of these operators in the executed program

The Kiel Esterel Processor - A Semi-Custom, Configurable Reactive Processor

The synchronous language Esterel is an established language for developing reactive systems. It gives an abstract, well-defined and executable description of the application, and can be synthesized into hardware and software. Typically, an Esterel program is first translated into other, lower-level languages (such as VHDL or C), and then compiled further. However, there is also the alternative of executing Esterel-like instructions directly. For example, in the REFLIX and RePIC projects, Roop et al. have augmented traditional processors with custom hardware to execute Esterel instructions. This patch strategy is a convenient approach, but has some shortages. We present the Kiel Esterel Processor (KEP), a semi-custom, configurable reactive processor for the direct execution of Esterel programs. It consists of a reactive core and scalable peripheral elements. KEP supports standard Esterel statements directly, except (so far) for the concurrency operator. Valued signals and counter functions in Esterel statements are supported by KEP. Due to its control path and its cooperation with elements, KEP obeys exact Esterel (preemption and priority) rules, including for example abort/weak abort (nests)

Challenges in Synthesizing Fast Control-Dominated Circuits

Presenting designers with higher-level specification languages is one sure way to improve productivity, but the more abstract the language, the higher the compiler's optimization burden. We consider generating efficient controller circuits from descriptions written in Esterel. To understand the demands of scalable optimization algorithms, we manually matched the results from sequential synthesis algorithms that produce good circuits but are costly or impossible to run on large designs. We hoped the high-level structure of Esterel would suggest inexpensive, effective optimizations, but our results are mixed. In the five examples we considered, many optimizations clearly could be automated cheaply, but we needed more global information to match the quality of the existing automatic techniques. This suggests an effective solution would have to combine both local and (potentially costly) global techniques

EPICURE: A partitioning and co-design framework for reconfigurable computing

This paper presents a new design methodology able to bridge the gap between an abstract specification and a heterogeneous reconfigurable architecture. The EPICURE contribution is the result of a joint study on abstraction/refinement methods and a smart reconfigurable architecture within the formal Esterel design tools suite. The original points of this work are: (i) a generic HW/SW interface model, (ii) a specification methodology that handles the control, and includes efficient verification and HW/SW synthesis capabilities, (iii) a method for parallelism exploration based on abstract resources/performance estimation expressed in terms of area/delay tradeoffs, (iv) a HW/SW partitioning approach that refines the specification into explicit HW configurations and the associated SW control. The EPICURE framework shows how a cooperation of complementary methodologies and CAD tools associated with a relevant architecture can signficantly improve the designer productivity, especially in the context of reconfigurable architectures