Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic

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Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement

Enabling Intra-Plane Parallel Block Erase to Alleviate the Impact of Garbage Collection

Garbage collection (GC) in NAND flash can significantly decrease I/O performance in SSDs by copying valid data to other locations, thus blocking incoming I/O requests. To help improve performance, NAND flash utilizes various advanced commands to increase internal parallelism. Currently, these commands only parallelize operations across channels, chips, dies, and planes, neglecting the block-level and below due structural bottlenecks along the data path and risk of disturbances that can compromise valid data by inducing errors. However, due to the triple-well structure of the NAND flash plane architecture and erasing procedure, it is possible to erase multiple blocks within a plane, in parallel, without being restricted by structural limitations or diminishing the integrity of the valid data. The number of page movements due to multiple block erases can be restrained so as to bound the overhead per GC. Moreover, more capacity can be reclaimed per GC which delays future GCs and effectively reduces their frequency. Such an Intra-Plane Parallel Block Erase (IPPBE) in turn diminishes the impact of GC on incoming requests, improving their response times. Experimental results show that IPPBE can reduce the time spent performing GC by up to 50.7% and 33.6% on average, read/write response time by up to 47.0%/45.4% and 16.5%/14.8% on average respectively, page movements by up to 52.2% and 26.6% on average, and blocks erased by up to 14.2% and 3.6% on average. An energy analysis conducted indicates that by reducing the number of page copies and the number of block erases, the energy cost of garbage collection can be reduced up to 44.1% and 19.3% on average

Tunnel Field Effect Transistors:from Steep-Slope Electronic Switches to Energy Efficient Logic Applications

The aim of this work has been the investigation of homo-junction Tunnel Field Effect Transistors starting from a compact modelling perspective to its possible applications. Firstly a TCAD based simulation study is done to explain the main device characteristics. The main differences of a Tunnel FET with respect to a conventional MOSFET is pointed out and the differences have been explained. A compact DC/AC model has been developed which is capable of describing the I-V characteristics in all regimes of operation. The model takes in to account ambi-polarity, drain side breakdown and all tunneling related physics. A temperature dependence is also added to the model to study the temperature independent behavior of tunneling. The model was further implemented in a Verilog-A based circuit simulator. Following calibration to experimental results of Silicon and strained-Silicon TFETs, the model has been also used to benchmark against a standard CMOS node for digital and analog applications. The circuits built with Tunnel FETs showed interesting temperature behavior which was superior to the compared CMOS node. In the same work, we also explore and propose solutions for using TFETs for low power memory applications. Both volatile and non-volatile memory concepts are investigated and explored. The application of a Tunnel FET as a capacitor-less memory has been experimentally demonstrated for the first time. New device concepts have been proposed and process flows for the same are developed to realize them in the clean room in EPFL

Design, Modeling and Analysis of Non-classical Field Effect Transistors

Transistor scaling following per Moore\u27s Law slows down its pace when entering into nanometer regime where short channel effects (SCEs), including threshold voltage fluctuation, increased leakage current and mobility degradation, become pronounced in the traditional planar silicon MOSFET. In addition, as the demand of diversified functionalities rises, conventional silicon technologies cannot satisfy all non-digital applications requirements because of restrictions that stem from the fundamental material properties. Therefore, novel device materials and structures are desirable to fuel further evolution of semiconductor technologies. In this dissertation, I have proposed innovative device structures and addressed design considerations of those non-classical field effect transistors for digital, analog/RF and power applications with projected benefits. Considering device process difficulties and the dramatic fabrication cost, application-oriented device design and optimization are performed through device physics analysis and TCAD modeling methodology to develop design guidelines utilizing transistor\u27s improved characteristics toward application-specific circuit performance enhancement. Results support proposed device design methodologies that will allow development of novel transistors capable of overcoming limitation of planar nanoscale MOSFETs. In this work, both silicon and III-V compound devices are designed, optimized and characterized for digital and non-digital applications through calibrated 2-D and 3-D TCAD simulation. For digital functionalities, silicon and InGaAs MOSFETs have been investigated. Optimized 3-D silicon-on-insulator (SOI) and body-on-insulator (BOI) FinFETs are simulated to demonstrate their impact on the performance of volatile memory SRAM module with consideration of self-heating effects. Comprehensive simulation results suggest that the current drivability degradation due to increased device temperature is modest for both devices and corresponding digital circuits. However, SOI FinFET is recommended for the design of low voltage operation digital modules because of its faster AC response and better SCEs management than the BOI structure. The FinFET concept is also applied to the non-volatile memory cell at 22 nm technology node for low voltage operation with suppressed SCEs. In addition to the silicon technology, our TCAD estimation based on upper projections show that the InGaAs FinFET, with superior mobility and improved interface conditions, achieve tremendous drive current boost and aggressively suppressed SCEs and thereby a strong contender for low-power high-performance applications over the silicon counterpart. For non-digital functionalities, multi-fin FETs and GaN HEMT have been studied. Mixed-mode simulations along with developed optimization guidelines establish the realistic application potential of underlap design of silicon multi-Fin FETs for analog/RF operation. The device with underlap design shows compromised current drivability but improve analog intrinsic gain and high frequency performance. To investigate the potential of the novel N-polar GaN material, for the first time, I have provided calibrated TCAD modeling of E-mode N-polar GaN single-channel HEMT. In this work, I have also proposed a novel E-mode dual-channel hybrid MIS-HEMT showing greatly enhanced current carrying capability. The impact of GaN layer scaling has been investigated through extensive TCAD simulations and demonstrated techniques for device optimization

Caractérisation, mécanismes et applications mémoire des transistors avancés sur SOI

Ce travail présente les principaux résultats obtenus avec une large gamme de dispositifs SOI avancés, candidats très prometteurs pour les futurs générations de transistors MOSFETs. Leurs propriétés électriques ont été analysées par des mesures systématiques, agrémentées par des modèles analytiques et/ou des simulations numériques. Nous avons également proposé une utilisation originale de dispositifs FinFETs fabriqués sur ONO enterré en fonctionnalisant le ONO à des fins d'application mémoire non volatile, volatile et unifiées. Après une introduction sur l'état de l'art des dispositifs avancés en technologie SOI, le deuxième chapitre a été consacré à la caractérisation détaillée des propriétés de dispositifs SOI planaires ultra- mince (épaisseur en dessous de 7 nm) et multi-grille. Nous avons montré l excellent contrôle électrostatique par la grille dans les transistors très courts ainsi que des effets intéressants de transport et de couplage. Une approche similaire a été utilisée pour étudier et comparer des dispositifs FinFETs à double grille et triple grille. Nous avons démontré que la configuration FinFET double grille améliore le couplage avec la grille arrière, phénomène important pour des applications à tension de seuil multiple. Nous avons proposé des modèles originaux expliquant l'effet de couplage 3D et le comportement de la mobilité dans des TFTs nanocristallin ZnO. Nos résultats ont souligné les similitudes et les différences entre les transistors SOI et à base de ZnO. Des mesures à basse température et de nouvelles méthodes d'extraction ont permis d'établir que la mobilité dans le ZnO et la qualité de l'interface ZnO/SiO2 sont remarquables. Cet état de fait ouvre des perspectives intéressantes pour l'utilisation de ce type de matériaux aux applications innovantes de l'électronique flexible. Dans le troisième chapitre, nous nous sommes concentrés sur le comportement de la mobilité dans les dispositifs SOI planaires et FinFET en effectuant des mesures de magnétorésistance à basse température. Nous avons mis en évidence expérimentalement un comportement de mobilité inhabituel (multi-branche) obtenu lorsque deux ou plusieurs canaux coexistent et interagissent. Un autre résultat original concerne l existence et l interprétation de la magnétorésistance géométrique dans les FinFETs.L'utilisation de FinFETs fabriqués sur ONO enterré en tant que mémoire non volatile flash a été proposée dans le quatrième chapitre. Deux mécanismes d'injection de charge ont été étudiés systématiquement. En plus de la démonstration de la pertinence de ce type mémoire en termes de performances (rétention, marge de détection), nous avons mis en évidence un comportement inattendu : l amélioration de la marge de détection pour des dispositifs à canaux courts. Notre concept innovant de FinFlash sur ONO enterré présente plusieurs avantages: (i) opération double-bit et (ii) séparation de la grille de stockage et de l'interface de lecture augmentant la fiabilité et autorisant une miniaturisation plus poussée que des Finflash conventionnels avec grille ONO.Dans le dernier chapitre, nous avons exploré le concept de mémoire unifiée, en combinant les opérations non volatiles et 1T-DRAM par le biais des FinFETs sur ONO enterré. Comme escompté pour les mémoires dites unifiées, le courant transitoire en mode 1T-DRAM dépend des charges non volatiles stockées dans le ONO. D'autre part, nous avons montré que les charges piégées dans le nitrure ne sont pas perturbées par les opérations de programmation et lecture de la 1T-DRAM. Les performances de cette mémoire unifiée multi-bits sont prometteuses et pourront être considérablement améliorées par optimisation technologique de ce dispositif.The evolution of electronic systems and portable devices requires innovation in both circuit design and transistor architecture. During last fifty years, the main issue in MOS transistor has been the gate length scaling down. The reduction of power consumption together with the co-integration of different functions is a more recent avenue. In bulk-Si planar technology, device shrinking seems to arrive at the end due to the multiplication of parasitic effects. The relay has been taken by novel SOI-like device architectures. In this perspective, this manuscript presents the main achievements of our work obtained with a variety of advanced fully depleted SOI MOSFETs, which are very promising candidates for next generation MOSFETs. Their electrical properties have been analyzed by systematic measurements and clarified by analytical models and/or simulations. Ultimately, appropriate applications have been proposed based on their beneficial features.In the first chapter, we briefly addressed the short-channel effects and the diverse technologies to improve device performance. The second chapter was dedicated to the detailed characterization and interesting properties of SOI devices. We have demonstrated excellent gate control and high performance in ultra-thin FD SOI MOSFET. The SCEs are efficiently suppressed by decreasing the body thickness below 7 nm. We have investigated the transport and electrostatic properties as well as the coupling mechanisms. The strong impact of body thickness and temperature range has been outlined. A similar approach was used to investigate and compare vertical double-gate and triple-gate FinFETs. DG FinFETs show enhanced coupling to back-gate bias which is applicable and suitable for dynamic threshold voltage tuning. We have proposed original models explaining the 3D coupling effect in FinFETs and the mobility behavior in ZnO TFTs. Our results pointed on the similarities and differences in SOI and ZnO transistors. According to our low-temperature measurements and new promoted extraction methods, the mobility in ZnO and the quality of ZnO/SiO2 interface are respectable, enabling innovating applications in flexible, transparent and power electronics. In the third chapter, we focused on the mobility behavior in planar SOI and FinFET devices by performing low-temperature magnetoresistance measurements. Unusual mobility curve with multi-branch aspect were obtained when two or more channels coexist and interplay. Another original result in the existence of the geometrical magnetoresistance in triple-gate and even double-gate FinFETs.The operation of a flash memory in FinFETs with ONO buried layer was explored in the forth chapter. Two charge injection mechanisms were proposed and systematically investigated. We have discussed the role of device geometry and temperature. Our novel ONO FinFlash concept has several distinct advantages: double-bit operation, separation of storage medium and reading interface, reliability and scalability. In the final chapter, we explored the avenue of unified memory, by combining nonvolatile and 1T-DRAM operations in a single transistor. The key result is that the transient current, relevant for 1T-DRAM operation, depends on the nonvolatile charges stored in the nitride buried layer. On the other hand, the trapped charges are not disturbed by the 1T-DRAM operation. Our experimental data offers the proof-of-concept for such advanced memory. The performance of the unified/multi-bit memory is already decent but will greatly improve in the coming years by processing dedicated devices.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash

[[abstract]]Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches[[notice]]補正完

신축성 있고 착용 가능한 탄소 나노튜브 기반 전자 기술

학위논문 (박사) -- 서울대학교 대학원 : 공과대학 협동과정 바이오엔지니어링전공, 2020. 8. 김대형.Networks of carbon nanotubes (CNTs) are a promising candidate for use as a basic building block for next-generation soft electronics, owing to their superior mechanical and electrical properties, chemical stability, and low production cost. In particular, the CNTs, which are produced as a mixture of metallic and semiconducting CNTs via chemical vapor deposition, can be sorted according to their electronic types, which makes them useful for specific purposes: semiconducting CNTs can be employed as channel materials in transistor-based applications and metallic CNTs as electrodes. However, the development of CNT-based electronics for soft applications is still at its infant stage, mainly limited by the lack of solid technologies for developing high-performance deformable devices whose electrical performances are comparable to those fabricated using conventional inorganic materials. In this regard, soft CNT electronics with high mechanical stability and electrical performances have been pursued. First, wearable nonvolatile memory modules and logic gates were fabricated by employing networks of semiconducting CNTs as the channel materials, with strain-tolerant device designs for high mechanical stability. The fabricated devices exhibited low operation voltages, high device-to-device uniformity, on/off ratios, and on-current density, while maintaining its performance during ~30% stretching after being mounted on the human skin. In addition, various functional logic gates verified the fidelity of the reported technology, and successful fabrication of non-volatile memory modules with wearable features has been reported for the first time at the time of publication. Second, the networks of semiconducting CNTs were used to fabricate signal amplifiers with a high gain of ~80, which were then used to amplify electrocardiogram (ECG) signals measured using a wearable sensor. At the same time, color-tunable organic light-emitting diodes (CTOLEDs) were developed based on ultra-thin charge blocking layer that controlled the flow of excitons during different voltage regimes. Together, they were integrated to construct a health monitoring platform whereby real-time ECG signals could be detected while simultaneously notifying its user of the ECG status via color changes of the wearable CTOLEDs. Third, intrinsically stretchable CNT transistors were developed, which was enabled by the developments of thickness controllable, vacuum-deposited stretchable dielectric layer and vacuum-deposited metal thin films. Previous works employed strain-tolerant device designs which are based on the use of filamentary serpentine-shaped interconnections, which severely sacrifice the device density. The developed stretchable dielectric, compatible with the current vacuum-based microfabrication technology, exhibited excellent insulating properties even for nanometer-range thicknesses, thereby enabling significant electrical performance improvements such as low operation voltage and high device uniformity/reproducibility, which has not been realized in the most advanced intrinsically stretchable transistors of today.탄소 나노튜브는 뛰어난 전기적, 화학적, 그리고 기계적 특성을 갖고 있어 차세대 유연 전자소자의 핵심 소재 중 하나로 각광을 받고 있으나, 아직까지 이를 이용한 실용적인 유연 전자소자의 개발은 실현되지 않고 있다. 이는 탄소 나노튜브의 전기적 특성대로 완벽히 분류해 낼 수 있는 기술, 탄소 나노튜브를 소자의 원하는 위치에 정확히 원하는 양만큼 네트워크 형태 혹은 정렬된 형태로 증착하는 기술, 그리고 유연 전자소자를 구성하는 다른 물질들의 개발 기술의 부재 때문이다. 지난 10여년간 해당 기술들은 광범위하게 연구되어지고 있으나, 탄소 나노튜브를 활용한 우수한 유연 전자소자 개발을 위한 핵심 기술들의 발전은 아직 초기 단계에 있다. 따라서 이 논문을 통해 탄소 나노튜브를 유연 전자소자에 적용시킬 수 있는 새로운 기술을 소개하고자 한다. 첫번째로 탄소 나노튜브와 유연 전자소자의 소자 디자인을 이용하여 피부위에 증착 가능한 비휘발성 메모리 소자를 제작하였고, 해당 기술을 이용하여 피부위에서 안전하게 동작할 수 있는 다양한 기초 회로들을 구현하였다. 탄소 나노튜브 기반 메모리 전자 소자 및 회로는 다양한 외부 응력이 가해져도 안정적으로 동작을 하였고, 개발된 기술을 통해 보다 실용적인 탄소 나노튜브 기반 유연 전자 소자의 제작 조건을 확립할 수 있었다. 두번째로 위에 개발된 기술을 바탕으로, 보다 복잡한 탄소 나노튜브 기반 유연 회로 및 구동전압에 따라 발광색이 변환하는 색변환 소자를 제작하여 해당 소자들이 피부위에 부착되어 잘 작동되도록 구현하였다. 그리고 이 두 가지 웨어러블 전자소자를 통합하여 실시간으로 심전도를 측정하여 탄소 나노튜브 기반 전자소자를 통해 해당 신호를 증폭시키고, 신호의 상태를 색변환 소자로 나타낼 수 있는 심전도 모니터 시스템을 구현하였다. 세번째로 진공 증착이 가능한 유연 절연체를 개발하여, 기존의 유연 전자소자들이 가지고 있던 극명한 한계를 극복하였다 (높은 구동 전압, 낮은 집적도, 대면적 소자 선능 균일도 등). 기존의 액상 기반 증착을 위주로 한 유연 전자 소자들은 무기물질 기반 전자소자 대비 극심한 성능 저하를 보여주었는데, 이를 해결하기 위해 새로운 절연물질을 개발하고 탄소 나노튜브 기반 유연 전자소자에 적용하여 그 가능성을 보여주었다.Chapter 1. Introduction 1 1.1 Discovery of CNTs and their benefits for soft electronic applications 1 1.2 Electrical sorting of CNTs 5 1.3 Deposition methods of solution-processed semiconducting CNTs 7 1.4 Conclusion 23 1.5 References 24 Chapter 2. Stretchable Carbon Nanotube Charge-Trap Floating-Gate Memory and Logic Devices for Wearable Electronics 32 2.1 Introduction 32 2.2 Experimental section 34 2.3 Results and discussion 36 2.4 Conclusion 62 2.5 References 63 Chapter 3. Wearable Electrocardiogram Monitor Using Carbon Nanotube Electronics and Color-Tunable Organic Light-Emitting Diodes 67 3.1 Introduction 67 3.2 Experimental section 70 3.3 Results and discussion 73 3.4 Conclusion 97 3.5 References 98 Chapter 4. Medium-Scale Electronic Skin Based on Carbon Nanotube Transistors with Vacuum-Deposited Stretchable Dielectric Film 102 4.1 Introduction 102 4.2 Experimental section 106 4.3 Result and discussion 111 4.4 Conclusion 135 4.5 References 136Docto

Evaluation of the colossal electroresistance (CER) effect and its application in the non-volatile Resistive Random Access Memory (RRAM)

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Materials Science and Engineering, 2009.Cataloged from PDF version of thesis.Includes bibliographical references (p. 79-81).Flash memory, the current leading technology for non-volatile memory (NVM), is projected by many to run obsolete in the face of future miniaturization trend in the semiconductor devices due to some of its technical limitations. Several different technologies have been developed in attempt for replacing Flash memory as the most dominant NVM technology; none of which seems to indicate significant success at the moment. Among these technologies is RRAM (Resistive Random Access Memory), a novel type of memory technology which has only recently emerged to join the race. The underlying principle of an RRAM device is based on the colossal electroresistance (CER) effect, i.e. the resistance switching behavior upon application of voltage of varying polarity and/or magnitude. This thesis aims to investigate the CER effect and how it can be designed to be a non-volatile memory as well as other novel application, e.g. memristor. The various technical aspects pertaining to this phenomenon, including the materials and the physical basis, are explored and analyzed. As a complementary to that, the market potential of the RRAM technology is also assessed. This includes the market study of memory industry, the current intellectual property (IP) landscape and some of the relevant business strategies. The production strategy (i.e. the production cost, initial investment, and pricing strategy) is then derived from the technical and market analysis evaluated earlier and with using some reasonable assumptions.by Aulia Tegar Wicaksono.M.Eng

Advances in Solid State Circuit Technologies

This book brings together contributions from experts in the fields to describe the current status of important topics in solid-state circuit technologies. It consists of 20 chapters which are grouped under the following categories: general information, circuits and devices, materials, and characterization techniques. These chapters have been written by renowned experts in the respective fields making this book valuable to the integrated circuits and materials science communities. It is intended for a diverse readership including electrical engineers and material scientists in the industry and academic institutions. Readers will be able to familiarize themselves with the latest technologies in the various fields