Evolution of Test Programs Exploiting a FSM Processor Model

Microprocessor testing is becoming a challenging task, due to the increasing complexity of modern architectures. Nowadays, most architectures are tackled with a combination of scan chains and Software-Based Self-Test (SBST) methodologies. Among SBST techniques, evolutionary feedback-based ones prove effective in microprocessor testing: their main disadvantage, however, is the considerable time required to generate suitable test programs. A novel evolutionary-based approach, able to appreciably reduce the generation time, is presented. The proposed method exploits a high-level representation of the architecture under test and a dynamically built Finite State Machine (FSM) model to assess fault coverage without resorting to time-expensive simulations on low-level models. Experimental results, performed on an OpenRISC processor, show that the resulting test obtains a nearly complete fault coverage against the targeted fault mode

Post-silicon failing-test generation through evolutionary computation

The incessant progress in manufacturing technology is posing new challenges to microprocessor designers. Several activities that were originally supposed to be part of the pre-silicon design phase are migrating after tape-out, when the first silicon prototypes are available. The paper describes a post-silicon methodology for devising functional failing tests. Therefore, suited to be exploited by microprocessor producer to detect, analyze and debug speed paths during verification, speed-stepping, or other critical activities. The proposed methodology is based on an evolutionary algorithm and exploits a versatile toolkit named µGP. The paper describes how to take into account complex hardware characteristics and architectural details of such complex devices. The experimental evaluation clearly demonstrates the potential of this line of researc

Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation

Detailed modeling of processors and high performance cycle-accurate simulators are essential for today's hardware and software design. These problems are challenging enough by themselves and have seen many previous research efforts. Addressing both simultaneously is even more challenging, with many existing approaches focusing on one over another. In this paper, we propose the Reduced Colored Petri Net (RCPN) model that has two advantages: first, it offers a very simple and intuitive way of modeling pipelined processors; second, it can generate high performance cycle-accurate simulators. RCPN benefits from all the useful features of Colored Petri Nets without suffering from their exponential growth in complexity. RCPN processor models are very intuitive since they are a mirror image of the processor pipeline block diagram. Furthermore, in our experiments on the generated cycle-accurate simulators for XScale and StrongArm processor models, we achieved an order of magnitude (~15 times) speedup over the popular SimpleScalar ARM simulator.Comment: Submitted on behalf of EDAA (http://www.edaa.com/

Preliminary candidate advanced avionics system for general aviation

An integrated avionics system design was carried out to the level which indicates subsystem function, and the methods of overall system integration. Sufficient detail was included to allow identification of possible system component technologies, and to perform reliability, modularity, maintainability, cost, and risk analysis upon the system design. Retrofit to older aircraft, availability of this system to the single engine two place aircraft, was considered

Aerospace medicine and biology: A continuing bibliography with indexes, supplement 204

This bibliography lists 140 reports, articles, and other documents introduced into the NASA scientific and technical information system in February 1980

Integration of a cellular Internet-of-Things transceiver into 6G test network and evaluation of its performance

Abstract. This thesis focuses on the integration and deployment of an aftermarket cellular IoT transceiver on a 6G/5G test network for the purpose of evaluating the feasibility of such device for monitoring the network performance. The cellular technology employed was NB-IoT paired with a Raspberry Pi device as the microprocessor that collects network telemetry and uses MQTT protocol to provide constant data feed. The system was first tested in a public cellular network through a local service provider and was successfully connected to the network, establishing TCP/IP connections, and allowing internet connectivity. To monitor network information and gathering basic telemetry data, a network monitoring utility was developed. It collected data such as network identifiers, module registration status, band/channel, signal strength and GPS position. This data was then published to a MQTT broker. The Adafruit IO platform served as the MQTT broker, providing an interface to visualize the collected data. Furthermore, the system was configured for and deployed on a 6G/5G test network successfully. The device functionality that was developed and tested in the public network remained intact, enabling continuous monitoring and analysis of network data. Through this study, valuable insights into the integration and deployment of cellular IoT transceivers into cellular networks that employ the latest IoT technology were gained. The findings highlight the feasibility of utilizing such a system for network monitoring and demonstrate the potential for IoT applications in cellular networks