443 research outputs found

    An Optoelectronic Stimulator for Retinal Prosthesis

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    Retinal prostheses require the presence of viable population of cells in the inner retina. Evaluations of retina with Age-Related Macular Degeneration (AMD) and Retinitis Pigmentosa (RP) have shown a large number of cells remain in the inner retina compared with the outer retina. Therefore, vision loss caused by AMD and RP is potentially treatable with retinal prostheses. Photostimulation based retinal prostheses have shown many advantages compared with retinal implants. In contrary to electrode based stimulation, light does not require mechanical contact. Therefore, the system can be completely external and not does have the power and degradation problems of implanted devices. In addition, the stimulating point is flexible and does not require a prior decision on the stimulation location. Furthermore, a beam of light can be projected on tissue with both temporal and spatial precision. This thesis aims at fi nding a feasible solution to such a system. Firstly, a prototype of an optoelectronic stimulator was proposed and implemented by using the Xilinx Virtex-4 FPGA evaluation board. The platform was used to demonstrate the possibility of photostimulation of the photosensitized neurons. Meanwhile, with the aim of developing a portable retinal prosthesis, a system on chip (SoC) architecture was proposed and a wide tuning range sinusoidal voltage-controlled oscillator (VCO) which is the pivotal component of the system was designed. The VCO is based on a new designed Complementary Metal Oxide Semiconductor (CMOS) Operational Transconductance Ampli er (OTA) which achieves a good linearity over a wide tuning range. Both the OTA and the VCO were fabricated in the AMS 0.35 µm CMOS process. Finally a 9X9 CMOS image sensor with spiking pixels was designed. Each pixel acts as an independent oscillator whose frequency is controlled by the incident light intensity. The sensor was fabricated in the AMS 0.35 µm CMOS Opto Process. Experimental validation and measured results are provided

    Investigation of high bandwith biodevices for transcutaneous wireless telemetry

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    PhD ThesisBIODEVICE implants for telemetry are increasingly applied today in various areas applications. There are many examples such as; telemedicine, biotelemetry, health care, treatments for chronic diseases, epilepsy and blindness, all of which are using a wireless infrastructure environment. They use microelectronics technology for diagnostics or monitoring signals such as Electroencephalography or Electromyography. Conceptually the biodevices are defined as one of these technologies combined with transcutaneous wireless implant telemetry (TWIT). A wireless inductive coupling link is a common way for transferring the RF power and data, to communicate between a reader and a battery-less implant. Demand for higher data rate for the acquisition data returned from the body is increasing, and requires an efficient modulator to achieve high transfer rate and low power consumption. In such applications, Quadrature Phase Shift Keying (QPSK) modulation has advantages over other schemes, and double the symbol rate with respect to Binary Phase Shift Keying (BPSK) over the same spectrum band. In contrast to analogue modulators for generating QPSK signals, where the circuit complexity and power dissipation are unsuitable for medical purposes, a digital approach has advantages. Eventually a simple design can be achieved by mixing the hardware and software to minimize size and power consumption for implantable telemetry applications. This work proposes a new approach to digital modulator techniques, applied to transcutaneous implantable telemetry applications; inherently increasing the data rate and simplifying the hardware design. A novel design for a QPSK VHDL modulator to convey a high data rate is demonstrated. Essentially, CPLD/FPGA technology is used to generate hardware from VHDL code, and implement the device which performs the modulation. This improves the data transmission rate between the reader and biodevice. This type of modulator provides digital synthesis and the flexibility to reconfigure and upgrade with the two most often languages used being VHDL and Verilog (IEEE Standard) being used as hardware structure description languages. The second objective of this thesis is to improve the wireless coupling power (WCP). An efficient power amplifier was developed and a new algorithm developed for auto-power control design at the reader unit, which monitors the implant device and keeps the device working within the safety regulation power limits (SAR). The proposed system design has also been modeled and simulated with MATLAB/Simulink to validate the modulator and examine the performance of the proposed modulator in relation to its specifications.Higher Education Ministry in Liby

    Energy-Efficient Wireless Interconnect Design for Non-Destructive Testing (NDT) Applications

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    A method for non-destructive, wireless testing of integrated circuits(ICs) is presented in this thesis. This system is suitable for applications which require testing after the manufacturing of ICs. According to Moore\u27s Law the number of transistors in an IC doubles every two years, the current probing equipment will also have to reduce its size accordingly which will be difficult after a certain point. The proposed system relies on near field communication in order to transfer data between probe and device under test. The probe and IC will include small antenna and a transceiver circuit. The antenna and the transceiver circuit can be integrated into the device without affecting the real estate and performance. Major advantages of non-destructive probing include no damage to the pads of test chip, higher test frequencies and less maintenance which will lead to higher pin densities. The antenna and transceiver circuit to be incorporated on the test chip are completely CMOS compliant.;The presented system here is a prototype which consists of a transceiver circuit along with an ultra-wideband antenna. The system was implemented in IBM 180nm CMOS process. The transceiver circuit communicates at a high frequency of 21.5GHz which in turn reduces the area consumed by the antenna and the transceiver circuit. The results obtained for our system show that an energy efficient wireless interconnect has been successfully implemented for future non-destructive testing applications

    GigaHertz Symposium 2010

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    Acceleration Techniques for Sparse Recovery Based Plane-wave Decomposition of a Sound Field

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    Plane-wave decomposition by sparse recovery is a reliable and accurate technique for plane-wave decomposition which can be used for source localization, beamforming, etc. In this work, we introduce techniques to accelerate the plane-wave decomposition by sparse recovery. The method consists of two main algorithms which are spherical Fourier transformation (SFT) and sparse recovery. Comparing the two algorithms, the sparse recovery is the most computationally intensive. We implement the SFT on an FPGA and the sparse recovery on a multithreaded computing platform. Then the multithreaded computing platform could be fully utilized for the sparse recovery. On the other hand, implementing the SFT on an FPGA helps to flexibly integrate the microphones and improve the portability of the microphone array. For implementing the SFT on an FPGA, we develop a scalable FPGA design model that enables the quick design of the SFT architecture on FPGAs. The model considers the number of microphones, the number of SFT channels and the cost of the FPGA and provides the design of a resource optimized and cost-effective FPGA architecture as the output. Then we investigate the performance of the sparse recovery algorithm executed on various multithreaded computing platforms (i.e., chip-multiprocessor, multiprocessor, GPU, manycore). Finally, we investigate the influence of modifying the dictionary size on the computational performance and the accuracy of the sparse recovery algorithms. We introduce novel sparse-recovery techniques which use non-uniform dictionaries to improve the performance of the sparse recovery on a parallel architecture

    Process-tolerant VLSI neural networks for applications in optimisation

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    Algorithm and Architecture Co-design for High-performance Digital Signal Processing.

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    CMOS scaling has been the driving force behind the revolution of digital signal processing (DSP) systems, but scaling is slowing down and the CMOS device is approaching its fundamental scaling limit. At the same time, DSP algorithms are continuing to evolve, so there is a growing gap between the increasing complexities of the algorithms and what is practically implementable. The gap can be bridged by exploring the synergy between algorithm and hardware design, using the so-called co-design techniques. In this thesis, algorithm and architecture co-design techniques are applied to X-ray computed tomography (CT) image reconstruction. Analysis of fixed-point quantization and CT geometry identifies an optimal word length and a mismatch between the object and projection grids. A water-filling buffer is designed to resolve the grid mismatch, and is combined with parallel fixed-point arithmetic units to improve the throughput. The analysis eventually leads to an out-of-order scheduling architecture that reduces the off-chip memory access by three orders of magnitude. The co-design techniques are further applied to the design of neural networks for sparse coding. Analysis of the neuron spiking dynamics leads to the optimal tuning of network size, spiking rate, and update step size to keep the spiking sparse. The resulting sparsity enables a bus-ring architecture to achieve both high throughput and scalability. A 65nm CMOS chip implementing the architecture demonstrates feature extraction at a throughput of 1.24G pixel/s at 1.0V and 310MHz. The error tolerance of sparse coding can be exploited to enhance the energy efficiency. As a natural next step after the sparse coding chip, a neural-inspired inference module (IM) is designed for object recognition. The object recognition chip consists of an IM based on sparse coding and an event-driven classifier. A learning co-processor is integrated on chip to enable on-chip learning. The throughput and energy efficiency are further improved using architectural techniques including sub-dividing the IM and classifier into modules and optimal pipelining. The result is a 65nm CMOS chip that performs sparse coding at 10.16G pixel/s at 1.0V and 635MHz. The co-design techniques can be applied to the design of other advanced DSP algorithms for emerging applications.PhDElectrical Engineering: SystemsUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/113344/1/jungkook_1.pd

    Applications in Electronics Pervading Industry, Environment and Society

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    This book features the manuscripts accepted for the Special Issue “Applications in Electronics Pervading Industry, Environment and Society—Sensing Systems and Pervasive Intelligence” of the MDPI journal Sensors. Most of the papers come from a selection of the best papers of the 2019 edition of the “Applications in Electronics Pervading Industry, Environment and Society” (APPLEPIES) Conference, which was held in November 2019. All these papers have been significantly enhanced with novel experimental results. The papers give an overview of the trends in research and development activities concerning the pervasive application of electronics in industry, the environment, and society. The focus of these papers is on cyber physical systems (CPS), with research proposals for new sensor acquisition and ADC (analog to digital converter) methods, high-speed communication systems, cybersecurity, big data management, and data processing including emerging machine learning techniques. Physical implementation aspects are discussed as well as the trade-off found between functional performance and hardware/system costs

    Displays, memories, and signal processing: A compilation

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    Articles on electronics systems and techniques were presented. The first section is on displays and other electro-optical systems; the second section is devoted to signal processing. The third section presented several new memory devices for digital equipment, including articles on holographic memories. The latest patent information available is also given

    Programmable rate modem utilizing digital signal processing techniques

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    The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery
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