Design Considerations of a Sub-50 {\mu}W Receiver Front-end for Implantable Devices in MedRadio Band

Emerging health-monitor applications, such as information transmission through multi-channel neural implants, image and video communication from inside the body etc., calls for ultra-low active power (<50${\mu}$W) high data-rate, energy-scalable, highly energy-efficient (pJ/bit) radios. Previous literature has strongly focused on low average power duty-cycled radios or low power but low-date radios. In this paper, we investigate power performance trade-off of each front-end component in a conventional radio including active matching, down-conversion and RF/IF amplification and prioritize them based on highest performance/energy metric. The analysis reveals 50${\Omega}$ active matching and RF gain is prohibitive for 50${\mu}$W power-budget. A mixer-first architecture with an N-path mixer and a self-biased inverter based baseband LNA, designed in TSMC 65nm technology show that sub 50${\mu}$W performance can be achieved up to 10Mbps (< 5pJ/b) with OOK modulation.Comment: Accepted to appear on International Conference on VLSI Design 2018 (VLSID

Energy-Aware Low-Power CMOS LNA with Process-Variations Management

A reconfigurable low-noise amplifier (LNA) with digitally controllable gain and power consumption is presented.This architecture allows increasing power consumption only when required, that is, to improve LNA’s radiofrequency performance at extreme communication-channel conditions and/or to counteract the effect of process, voltage, and temperature variations.The proposed design leads to significant power saving when a relaxed operation is acceptable. The LNA is implemented in a 130nm 1.2V CMOS technology for a 2.4GHz IEEE-802.15.4 application. Simulated LNAperformance (taking into account theworst cases under process variations) is comparable to recently published worksCAPES-Brazil 176/12Ministerio de Asuntos Exteriores y Cooperación D/024124/09Junta de Andalucía P09-TIC- 5386Ministerio de Economía y Competitividad TEC2011-2830

Design Concepts of Low-Noise Amplifier for Radio Frequency Receivers

The development of high-performance radio frequency (RF) transceivers or multi-standard/reconfigurable receivers requires an innovative RF front-end design to ensure the best from a good technology. In general, the performance of front-end and/or building blocks can be improved only by an increase in the supply voltage, width of the transistors or an additional stage at the output of a circuit. This leads to increase the design issues like circuit size and the power consumption. Presently, the wireless market and the need to develop efficient portable electronic systems have pushed the industry to the production of circuit designs with low-voltage power supply. The objective of this work is to introduce an innovative single-stage design structure of low noise amplifier (LNA) to achieve higher performance under low operating voltage. TSMC 0.18 micron CMOS technology scale is utilized for realizing LNA designs and the simulation process is carried out with a supply voltage of 1.8 V. The LNA performance measures are analyzed by using an Intel Core2 duo CPU [email protected] processor with Agilent’s Advanced Design System (ADS) 2009 version software

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS

We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection technique leads to an architecture that compensates for the implementation loss of a low-power wake-up receiver front-end at low energy and area costs. Design parameters are selected by energy optimization and the architecture is easily scalable to support various network sizes. Fabricated in 65nm CMOS, the digital base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps, with appropriate 97% wake-up beacon detection and 0.04% false alarm probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at f_max=5kHz and 0.018uW power consumption. Based on these results we show that our digital base-band can be used as a companion to compensate for front-end implementation losses resulting from the limited wake-up receiver power budget at a negligible cost. This implies an improvement of the practical sensitivity of the wake-up receiver, compared to what is traditionally reported.Comment: Submitted to IEEE Sensors Journa

Energy-Efficient Wireless Circuits and Systems for Internet of Things

As the demand of ultra-low power (ULP) systems for internet of thing (IoT) applications has been increasing, large efforts on evolving a new computing class is actively ongoing. The evolution of the new computing class, however, faced challenges due to hard constraints on the RF systems. Significant efforts on reducing power of power-hungry wireless radios have been done. The ULP radios, however, are mostly not standard compliant which poses a challenge to wide spread adoption. Being compliant with the WiFi network protocol can maximize an ULP radio’s potential of utilization, however, this standard demands excessive power consumption of over 10mW, that is hardly compatible with in ULP systems even with heavy duty-cycling. Also, lots of efforts to minimize off-chip components in ULP IoT device have been done, however, still not enough for practical usage without a clean external reference, therefore, this limits scaling on cost and form-factor of the new computer class of IoT applications. This research is motivated by those challenges on the RF systems, and each work focuses on radio designs for IoT applications in various aspects. First, the research covers several endeavors for relieving energy constraints on RF systems by utilizing existing network protocols that eventually meets both low-active power, and widespread adoption. This includes novel approaches on 802.11 communication with articulate iterations on low-power RF systems. The research presents three prototypes as power-efficient WiFi wake-up receivers, which bridges the gap between industry standard radios and ULP IoT radios. The proposed WiFi wake-up receivers operate with low power consumption and remain compatible with the WiFi protocol by using back-channel communication. Back-channel communication embeds a signal into a WiFi compliant transmission changing the firmware in the access point, or more specifically just the data in the payload of the WiFi packet. With a specific sequence of data in the packet, the transmitter can output a signal that mimics a modulation that is more conducive for ULP receivers, such as OOK and FSK. In this work, low power mixer-first receivers, and the first fully integrated ultra-low voltage receiver are presented, that are compatible with WiFi through back-channel communication. Another main contribution of this work is in relieving the integration challenge of IoT devices by removing the need for external, or off-chip crystals and antennas. This enables a small form-factor on the order of mm3-scale, useful for medical research and ubiquitous sensing applications. A crystal-less small form factor fully integrated 60GHz transceiver with on-chip 12-channel frequency reference, and good peak gain dual-mode on-chip antenna is presented.PHDElectrical and Computer EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/162975/1/jaeim_1.pd

2.4 GHZ HETERODYNE RECEIVER FOR HEALTHCARE APPLICATION

Objective: The objective of this research was to design a basic 2.4 GHz heterodyne receiver for healthcare on a 130 um CMOS process. The ultimate goal for the wireless industry is to minimize the trade-offs between performance and cost, and between performance and low power consumption design.Methods: In the first part, a low noise amplifier (LNA), which is commonly used as the first stage of a receiver, is introduced and simulated. LNA performance greatly affects the overall receiver performance. The LNA was designed at the 2.4 GHz ISM band, using the cascode with an inductive degeneration topology. The second part of this proposal presents a low power 2.4 GHz down conversion Gilbert Cell mixer. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The design uses using PMOS cross-coupled topology with the varactor for wider tuning range topology.Results: In the first part, a low noise amplifier (LNA) design reached the NF of 2 dB, had power consumption of 2.2 mW, and had a gain of 20dB. The second part of this proposal presented a low power 2.4 GHz down conversion Gilbert Cell mixer. The obtained result showed a conversion gain of 14.6 dB and power consumption of 8.2 mW at a 1.3V supply voltage. In the third part, a high-performance LC-tank CMOS VCO was designed at 2.4 GHz. The final simulation of the phase noise was-128 dBc/Hz, and the tuning range was 2.3 GHz-2.5 GHz while the total power consumption was 3.25 mW. Conclusion: The performance of the receiver meets the specification requirements of the desired standard.Keywords: LNA, healthcare, VCO, mixer, Heterodyne receive

A Recofigurable Tri-Band Interconnect for Future Network-On-Chip

The scaling of CMOS feature sizes has yielded the capability of integrating heterogeneous intellectual properties (IPs) like graphics processing units (GPUs), digital signal processors (DSPs) and central processing units (CPUs) on a single die. The collection of multiple IPs on a single die presents a problem of reliable communication due to congestion. The infrastructure that facilitates and manages communication among IPs is referred to as a network-on-chip (NoC). Its ultimate goal should be low latency with negligible power and area consumption. Unfortunately, as CMOS feature sizes have been scaling smaller, this has exacerbated latency and signal degradation due to increasing on-chip channel resistance. Furthermore, contemporary interfaces use baseband-only signaling and have critical limitations like exponential energy consumption, limited bandwidth and non-reconfigurable data access.;In this work, we propose an energy efficient tri-band (baseband + 2 RF bands) signaling interface that is capable of simultaneous bi-directional communication and reconfigurable data access. Additionally, communication is accomplished through a shared transmission line which reduces the overall number of global interconnections. As a result, this reduces area consumption and mitigates interconnection complexity. The primary signicance of this interconnect configuration compared to contemporary designs is an increase of bandwidth and energy efficiency.;The interconnect design is composed of a baseband transceiver and two RF (10Ghz and 20GHz) transceivers. The RF transceivers utilize amplitude-shift keying (ASK) modulation scheme. ASK modulation allows ease of circuit design, but most importantly it can be used for noncoherent communication, which we implemented in this system. Noncoherent ASK modulation is area conservative and power efficient since there is no longer a need for power-hungry frequency synthesizers. Moreover, noncoherent ASK demodulation accomplishes direct-down conversation through a passive self-mixer for additional power savings.;The results from our work show that a multi-band interconnect is a suitable remedy for future NoC communication that has been reaching its bandwidth limitation with baseband-only signaling. In conclusion, this work demonstrates a sustainable balance of energy efficiency and increased bandwidth for future on-chip interconnect designs

Design of a low-voltage CMOS RF receiver for energy harvesting sensor node

In this thesis a CMOS low-power and low-voltage RF receiver front-end is presented. The main objective is to design this RF receiver so that it can be powered by a piezoelectric energy harvesting power source, included in a Wireless Sensor Node application. For this type of applications the major requirements are: the low-power and low-voltage operation, the reduced area and cost and the simplicity of the architecture. The system key blocks are the LNA and the mixer, which are studied and optimized with greater detail, achieving a good linearity, a wideband operation and a reduced introduction of noise. A wideband balun LNA with noise and distortion cancelling is designed to work at a 0.6 V supply voltage, in conjunction with a double-balanced passive mixer and subsequent TIA block. The passive mixer operates in current mode, allowing a minimal introduction of voltage noise and a good linearity. The receiver analog front-end has a total voltage conversion gain of 31.5 dB, a 0.1 - 4.3 GHz bandwidth, an IIP3 value of -1.35 dBm, and a noise figure lower than 9 dB. The total power consumption is 1.9 mW and the die area is 305x134.5 m2, using a standard 130 nm CMOS technology