Dual-Input DC-to-DC Converter Topologies and Control Schemes

Dual-input DC-to-DC converters are power supplies that draw power from two sources simultaneously and deliver power to a single load, the ratio of power drawn from each source and be held constant with changes in the load. Applications for dual-input power supplies are computer systems, mobile systems using energy harvesting, and systems needing redundant power supplies. This writing covers the operation and control of dual-input DC-to-DC converters that implement a non-inverting buck-boost function and utilize only a single power path. Traditionally, a dual-input power supply is created by placing two standard power paths in parallel. This adds considerable control complexity associated with synchronizing the two converters. Four new power path topologies are presented: dual-input four-FET buck-boost, dual-input zeta, dual-input SEPIC, and alternate dual-input SEPIC. The single power path approaches require fewer components than the traditional approaches, however, the efficiency is slightly lower. These converters can be controlled using any of the standard power supply control approaches, including: voltage mode, current mode, and constant on-time. Each control method does need to be modified slightly. The biggest difference in the control of these converters is in the logic that is used to control the switches in the power path. The ratio of current drawn from each input source can be held constant and can be adjusted in an open loop fashion if some variability is allowed, otherwise a sensor and feedback control can be implemented to fix the input current or input power ratio

Nouvelles Architectures Hybrides (Logique / Mémoires Non-Volatiles et technologies associées.)

Les nouvelles approches de technologies mémoires permettront une intégration dite back-end, où les cellules élémentaires de stockage seront fabriquées lors des dernières étapes de réalisation à grande échelle du circuit. Ces approches innovantes sont souvent basées sur l'utilisation de matériaux actifs présentant deux états de résistance distincts. Le passage d'un état à l'autre est contrôlé en courant ou en tension donnant lieu à une caractéristique I-V hystérétique. Nos mémoires résistives sont composées d'argent en métal électrochimiquement actif et de sulfure amorphe agissant comme électrolyte. Leur fonctionnement repose sur la formation réversible et la dissolution d'un filament conducteur. Le potentiel d'application de ces nouveaux dispositifs n'est pas limité aux mémoires ultra-haute densité mais aussi aux circuits embarqués. En empilant ces mémoires dans la troisième dimension au niveau des interconnections des circuits logiques CMOS, de nouvelles architectures hybrides et innovantes deviennent possibles. Il serait alors envisageable d'exploiter un fonctionnement à basse énergie, à haute vitesse d'écriture/lecture et de haute performance telles que l'endurance et la rétention. Dans cette thèse, en se concentrant sur les aspects de la technologie de mémoire en vue de développer de nouvelles architectures, l'introduction d'une fonctionnalité non-volatile au niveau logique est démontrée par trois circuits hybrides: commutateurs de routage non volatiles dans un Field Programmable Gate Arrays, un 6T-SRAM non volatile, et les neurones stochastiques pour un réseau neuronal. Pour améliorer les solutions existantes, les limitations de la performances des dispositifs mémoires sont identifiés et résolus avec des nouveaux empilements ou en fournissant des défauts de circuits tolérants.Novel approaches in the field of memory technology should enable backend integration, where individual storage nodes will be fabricated during the last fabrication steps of the VLSI circuit. In this case, memory operation is often based upon the use of active materials with resistive switching properties. A topology of resistive memory consists of silver as electrochemically active metal and amorphous sulfide acting as electrolyte and relies on the reversible formation and dissolution of a conductive filament. The application potential of these new memories is not limited to stand-alone (ultra-high density), but is also suitable for embedded applications. By stacking these memories in the third dimension at the interconnection level of CMOS logic, new ultra-scalable hybrid architectures becomes possible which exploit low energy operation, fast write/read access and high performance with respect to endurance and retention. In this thesis, focusing on memory technology aspects in view of developing new architectures, the introduction of non-volatile functionality at the logic level is demonstrated through three hybrid (CMOS logic ReRAM devices) circuits: nonvolatile routing switches in a Field Programmable Gate Array, nonvolatile 6T-SRAMs, and stochastic neurons of an hardware neural network. To be competitive or even improve existing solutions, limitations on the memory devices performances are identified and solved by stack engineering of CBRAM devices or providing faults tolerant circuits.SAVOIE-SCD - Bib.électronique (730659901) / SudocGRENOBLE1/INP-Bib.électronique (384210012) / SudocGRENOBLE2/3-Bib.électronique (384219901) / SudocSudocFranceF

Systems Engineering for Silicon Photonic Devices

The increasing integration of digital information with our daily lives has led to the rise of big data, cloud computing, and the internet of things. The growth in these categories will lead to an exponential increase in the required capacity for data centers and high performance computation. Meanwhile, due to bottlenecks in data access caused by the limited energy and bandwidth scalability of electrical interconnects, computational speedup can no longer scale with demand. A better solution is necessary in order to increase computational performance and reduce the carbon footprint of our digital future. People have long thought of photonic interconnects, which can offer higher bandwidth, greater energy efficiency, and orders-of-magnitude distance scalability compared to electrical interconnects, as a solution to the data access bottleneck in chip, board, and datacenter scale networks. Over the past three decades we have seen impressive growth of photonic technology from theoretical predictions to high-performance commercially available devices. However, the dream of an all-optical interconnection network for use in CPU, Memory, and rack-to-rack datacenter interconnects is not yet realized. Many challenges and obstacles still have to be addressed. This work investigates these challenges and describe some of the ways to overcome them. First we will first examine the pattern sensitivity of microring modulators, which are likely to be found as the first element in an optical interconnect. My work will illustrate the advantage of using depletion mode modulators compared to injection mode modulators as the number of consecutive symbols in the data pattern increases. Next we will look at the problem of thermal initialization for microring demultiplexers near the output of the optical interconnect. My work demonstrates the fastest achieved initialization speed to-date for a microring based demultiplexer. I will also explore an thermal initialization and control method for microrings based on temperature measurement using a pn-junction. Finally, we will look at how to control and initialize microring and MZI based optical switch fabrics, which is the second element found in a optical interconnect. Work here will show the possibility of switching high-speed WDM datastreams through microring based switches, as well as methods to deal with the complexities inherent in control and initialization of high-radix switch topologies. Through these demonstrations I hope to show that the challenges facing optical interconnects, although very real, are surmountable using reasonable engineering efforts

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

Silicon Photonic Subsystems for Inter-Chip Optical Networks

The continuous growth of electronic compute and memory nodes in terms of the number of I/O pins, bandwidth, and areal throughput poses major integration and packaging challenges associated with offloading multi-Tbit/s data rates within the few pJ/bit targets. While integrated photonics are already deployed in long and short distances such as inter and intra data centers communications, the promising characteristics of the silicon photonic platform set it as the future technology for optical interconnects in ultra short inter-chip distances. The high index contrast between the waveguide and the cladding together with strong thermo-optic and carrier effects in silicon allows developing a wide range of micro-scale and low power optical devices compatible with the CMOS fabrication processes. Furthermore, the availability of photonic foundries and new electrical and optical co-packaging techniques further pushes this platform for the next steps of commercial deployment. The work in this dissertation presents the current trends in high-performance memory and processor nodes and gives motivation for disaggregated and reconfigurable inter-chip network enabled with the silicon photonic layer. A dense WDM transceiver and broadband switch architectures are discussed to support a bi-directional network of ten hybrid-memory cubes (HMC) interconnected to ten processor nodes with an overall aggregated bandwidth of 9.6Tbit/s. Latency and energy consumption are key performance parameters in a processor to primary memory nodes connectivity. The transceiver design is based on energy-efficient micro-ring resonators, and the broadband switch is constructed with 2x2 Mach-Zehnder elements for nano-second reconfiguration. Each transceiver is based on hundreds of micro-rings to convert the native HMC electrical protocol to the optical domain and the switch is based on tens of hundreds of 2x2 elements to achieve non-blocking all-to-all connectivity. The next chapters focus on developing methods for controlling and monitoring such complex and highly integrated silicon photonic subsystems. The thermo-optic effect is characterized and we show experimentally that the phase of the optical carrier can be reliably controlled with pulse-width modulation (PWM) signal, ultimately relaxing the need for hundreds of digital to analog converters (DACs). We further show that doped waveguide heaters can be utilized as \textit{in-line} optical power monitors by measuring photo-conductance current, which is an alternative for the conventional tapping and integration of photo-diodes. The next part concerned with a common cascaded micro-ring resonator in a WDM transceiver design. We develop on an FPGA control algorithm that abstracts the physical layer and takes user-defined inputs to set the resonances to the desired wavelength in a unicast and multicast transmission modes. The associated sensitivities of these silicon ring resonators are presented and addressed with three closed-loop solutions. We first show a closed-loop operation based on tapping the error signal from the drop port of the micro-ring. The second solution presents a resonance wavelength locking with a single digital I/O for control and feedback signals. Lastly, we leverage the photo-conductance effect and demonstrate the locking procedure using only the doped heater for both control and feedback purposes. To achieve the inter-chip reconfigurability we discuss recent advances of high-port-count SiP broadband switches for reconfigurable inter-chip networks. To ensure optimal operation in terms of low insertion loss, low cross-talk and high signal integrity per routing path, hundreds of 2x2 Mach-Zehnder elements need to be biased precisely for the cross and bar states. We address this challenge with a tapless and a design agnostic calibration approach based on the photo-conductance effect. The automated algorithm returns a look-up table for all for each 2x2 element and the associated calibrated biases. Each routing scenario is then tested for insertion loss, crosstalk and bit-error rate of 25Gbit/s 4-level pulse amplitude modulation signals. The last part utilizes the Mach-Zehnder interferometers in WDM transceiver applications. We demonstrate a polarization insensitive four-channel WDM receiver with 40Gbit/s per channel and a transmitter design generating 8-level pulse amplitude modulation signals at 30Gbit/s

Design of LCOS microdisplay backplanes for projection applications

De evolutie van licht emitterende diodes (LED) heeft ervoor gezorgd dat het op dit moment interessant wordt om deze componenten als lichtbron te gebruiken in projectiesystemen. LED’s hebben belangrijke voordelen vergeleken met klassieke booglampen. Ze zijn compact, ze hebben een veel grotere levensduur en ogenblikkelijke schakeltijden, ze werken op lage spanningen, etc. LED’s zijn smalbandig en kunnen een groterekleurenbereik realiseren. Ze hebben momenteel echter een beperkte helderheid. Naast de lichtbron is het type van de lichtklep ook bepalend voor de kwaliteit van een projectiesysteem. Er bestaan verschillende lichtkleptechnologieën waaronder die van de reflectieve LCOS-panelen. Deze lichtkleppen kunnen zeer hoge resoluties hebben en wordenvaak gebruikt in kwalitatieve, professionele projectiesystemen. LED’s zijn echter totaal verschillend van booglampen. Ze hebben een andere vorm, package, stralingspatroon, aansturing, fysische en thermische eigenschappen, etc. Hoewel er een twintigtal optische architecturen bekend zijn voor reflectieve beeldschermen (met een booglamp als lichtbron), zijn ze niet geschikt voor LED-projectoren en moeten nieuwe optische architecturen en een elektronische aansturing ontwikkeld worden. In dit doctoraat werd er hieromtrent onderzoek gedaan. Er werd uiteindelijk een driekleurenprojector (R, G, B) met een efficiënt LED-belichtingssysteem gebouwd met twee LCOS-lichtkleppen. Deze LEDprojector heeft superieure eigenschappen (zeer lange levensduur, beeldkwaliteit, etc.) en een matige lichtopbrengst

Pem fuel cell modeling and converters design for a 48 v dc power bus

Fuel cells (FC) are electrochemical devices that directly convert the chemical energy of a fuel into electricity. Power systems based on proton exchange membrane fuel cell (PEMFC) technology have been the object of increasing attention in recent years as they appear very promising in both stationary and mobile applications due to their high efficiency, low operating temperature allowing fast startup, high power density, solid electrolyte, long cell and stack life, low corrosion, excellent dynamic response with respect to the other FCs, and nonpolluting emissions to the environment if the hydrogen is obtained from renewable sources. The output-voltage characteristic in a PEMFC is limited by the mechanical devices which are used for regulating the air flow in its cathode, the hydrogen flow in its anode, its inner temperature, and the humidity of the air supplied to it. Usually, the FC time constants are dominated by the fuel delivery system, in particular by the slow dynamics of the compressor responsible for supplying the oxygen. As a consequence, a fast load transient demand could cause a high voltage drop in a short time known as oxygen starvation phenomenon that is harmful for the FC. Thus, FCs are considered as a slow dynamic response equipment with respect to the load transient requirements. Therefore, batteries, ultracapacitors or other auxiliary power sources are needed to support the operation of the FC in order to ensure a fast response to any load power transient. The resulting systems, known as FC hybrid systems, can limit the slope of the current or the power generated by the FC with the use of current-controlled dc-dc converters. In this way, the reactant gas starvation phenomena can be avoided and the system can operate with higher efficiency. The purpose of this thesis is the design of a DC-DC converter suitable to interconnect all the different elements in a PEMFC-hybrid 48-V DC bus. Since the converter could be placed between elements with very different voltage levels, a buck-boost structure has been selected. Especially to fulfill the low ripple requirements of the PEMFCs, but also those of the auxiliary storage elements and loads, our structure has inductors in series at both its input and its output. Magnetically coupling these inductors and adding a damping network to its intermediate capacitor we have designed an easily controllable converter with second-order-buck-like dominant dynamics. This new proposed topology has high efficiency and wide bandwidth acting either as a voltage or as a current regulator. The magnetic coupling allows to control with similar performances the input or the output inductor currents. This characteristic is very useful because the designed current-controlled converter is able to withstand shortcircuits at its output and, when connected to the FC, it facilitates to regulate the current extracted from the FC to avoid the oxygen starvation phenomenon. Testing in a safe way the converter connected to the FC required to build an FC simulator that was subsequently improved by developing an emulator that offered real-time processing and oxygen-starvation indication. To study the developed converters and emulators with different brands of PEMFCs it was necessary to reactivate long-time inactive Palcan FCs. Since the results provided by the manual reactivation procedure were unsatisfactory, an automatic reactivation system has been developed as a complementary study of the thesis.En esta tesis se avanzo en el diseño de un bus DC de 48 V que utiliza como elemento principal de generación de energía eléctrica una pila de combustible. Debido a que la dinámica de las pilas de combustible están limitadas por sus elementos mecánicos auxiliares de control una variación rápida de una carga conectada a ella puede ocasionar daños. Es por esto que es necesario utilizar elementos almacenadores de energía que puedan suministrar estas rápidas variaciones de carga y convertidores para que gestionen de una forma controlada la potencia del bus DC. Durante la realización de pruebas de los convertidores es de gran importancia utilizar emuladores o simuladores de pilas de combustibles, esto nos permite de una forma económica y segura realizar pruebas criticas antes de conectar los convertidores a la pila. Adicionalmente una nueva topologia de convertidor fue presentada y ésta gestionará la potencia en el bu

저전력, 저면적 유선 송수신기 설계를 위한 회로 기술

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 정덕균.In this thesis, novel circuit techniques for low-power and area-efficient wireline transceiver, including a phase-locked loop (PLL) based on a two-stage ring oscillator, a scalable voltage-mode transmitter, and a forwarded-clock (FC) receiver based on a delay-locked-loop (DLL) based per-pin deskew, are proposed. At first, a two-stage ring PLL that provides a four-phase, high-speed clock for a quarter-rate TX in order to minimize power consumption is presented. Several analyses and verification techniques, ranging from the clocking architectures for a high-speed TX to oscillation failures in a two-stage ring oscillator, are addressed in this thesis. A tri-state-inverter–based frequency-divider and an AC-coupled clock-buffer are used for high-speed operations with minimal power and area overheads. The proposed PLL fabricated in the 65-nm CMOS technology occupies an active area of 0.009 mm2 with an integrated-RMS-jitter of 414 fs from 10 kHz to 100 MHz while consuming 7.6 mW from a 1.2-V supply at 10 GHz. The resulting figure-of-merit is -238.8 dB, which surpasses that of the state-of-the-art ring-PLLs by 4 dB. Secondly, a voltage-mode (VM) transmitter which offers a wide operation range of 6 to 32 Gb/s, controllable pre-emphasis equalization and output voltage swing without altering output impedance, and a power supply scalability is presented. A quarter-rate clocking architecture is employed in order to maximize the scalability and energy efficiency across the variety of operating conditions. A P-over-N VM driver is used for CMOS compatibility and wide voltage-swing range required for various I/O standards. Two supply regulators calibrate the output impedance of the VM driver across the wide swing and pre-emphasis range. A single phase-locked loop is used to provide a wide frequency range of 1.5-to-8 GHz. The prototype chip is fabricated in 65-nm CMOS technology and occupies active area of 0.48x0.36 mm2. The proposed transmitter achieves 250-to-600-mV single-ended swing and exhibits the energy efficiency of 2.10-to-2.93 pJ/bit across the data rate of 6-to-32 Gb/s. And last, this thesis describes a power and area-efficient FC receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a DLL-based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-UIpp sinusoidal jitter of 300 MHz.Chapter 1. Introduction 1 1.1. Motivation 1 1.2. Thesis organization 5 Chapter 2. Phase-Locked Loop Based on Two-Stage Ring Oscillator 7 2.1. Overivew 7 2.2. Background and Analysis of a Two-stage Ring Oscillator 11 2.3. Circuit Implementation of The Proposed PLL 25 2.4. Measurement Results 33 Chapter 3. A Scalable Voltage-Mode Transmitter 37 3.1. Overview 37 3.2. Design Considerations on a Scalable Serial Link Transmitter 40 3.3. Circuit Implementation 46 3.4. Measurement Results 56 Chapter 4. Delay-Locked Loop Based Forwarded-Clock Receiver 62 4.1. Overview 62 4.2. Timing and Data Recovery in a Serial Link 65 4.3. DLL-Based Forwarded-Clock Receiver Characteristics 70 4.4. Circuit Implementation 79 4.5. Measurement Results 89 Chapter 5. Conclusion 94 Appendix 96 Appendix A. Design flow to optimize a high-speed ring oscillator 96 Appendix B. Reflection Issues in N-over-N Voltage-Mode Driver 99 Appendix C. Analysis on output swing and power consumption of the P-over-N voltage-mode driver 107 Appendix D. Loop Dynamics of DLL 112 Bibliography 121 Abstract 128Docto

A novel power management and control design framework for resilient operation of microgrids

This thesis concerns the investigation of the integration of the microgrid, a form of future electric grids, with renewable energy sources, and electric vehicles. It presents an innovative modular tri-level hierarchical management and control design framework for the future grid as a radical departure from the ‘centralised’ paradigm in conventional systems, by capturing and exploiting the unique characteristics of a host of new actors in the energy arena - renewable energy sources, storage systems and electric vehicles. The formulation of the tri-level hierarchical management and control design framework involves a new perspective on the problem description of the power management of EVs within a microgrid, with the consideration of, among others, the bi-directional energy flow between storage and renewable sources. The chronological structure of the tri-level hierarchical management operation facilitates a modular power management and control framework from three levels: Microgrid Operator (MGO), Charging Station Operator (CSO), and Electric Vehicle Operator (EVO). At the top level is the MGO that handles long-term decisions of balancing the power flow between the Distributed Generators (DGs) and the electrical demand for a restructure realistic microgrid model. Optimal scheduling operation of the DGs and EVs is used within the MGO to minimise the total combined operating and emission costs of a hybrid microgrid including the unit commitment strategy. The results have convincingly revealed that discharging EVs could reduce the total cost of the microgrid operation. At the middle level is the CSO that manages medium-term decisions of centralising the operation of aggregated EVs connected to the bus-bar of the microgrid. An energy management concept of charging or discharging the power of EVs in different situations includes the impacts of frequency and voltage deviation on the system, which is developed upon the MGO model above. Comprehensive case studies show that the EVs can act as a regulator of the microgrid, and can control their participating role by discharging active or reactive power in mitigating frequency and/or voltage deviations. Finally, at the low level is the EVO that handles the short-term decisions of decentralising the functioning of an EV and essential power interfacing circuitry, as well as the generation of low-level switching functions. EVO level is a novel Power and Energy Management System (PEMS), which is further structured into three modular, hierarchical processes: Energy Management Shell (EMS), Power Management Shell (PMS), and Power Electronic Shell (PES). The shells operate chronologically with a different object and a different period term. Controlling the power electronics interfacing circuitry is an essential part of the integration of EVs into the microgrid within the EMS. A modified, multi-level, H-bridge cascade inverter without the use of a main (bulky) inductor is proposed to achieve good performance, high power density, and high efficiency. The proposed inverter can operate with multiple energy resources connected in series to create a synergized energy system. In addition, the integration of EVs into a simulated microgrid environment via a modified multi-level architecture with a novel method of Space Vector Modulation (SVM) by the PES is implemented and validated experimentally. The results from the SVM implementation demonstrate a viable alternative switching scheme for high-performance inverters in EV applications. The comprehensive simulation results from the MGO and CSO models, together with the experimental results at the EVO level, not only validate the distinctive functionality of each layer within a novel synergy to harness multiple energy resources, but also serve to provide compelling evidence for the potential of the proposed energy management and control framework in the design of future electric grids. The design framework provides an essential design to for grid modernisation