Methods for Performance Evaluation of Parallel Computer Systems

Although parallel computers have existed for many years, recently there has been a surge of academic, industrial and governmental interest in parallel computing. Commercially manufactured parallel computers have started to become available. Many new experimental parallel architectures are reported in the literature every year. Software for many types of applications, from scientific number crunching to artificial intelligence, is being written to run on parallel machines. Performance is an essential consideration both in the design of new systems and the deployment of existing systems. Users of computers wish to utilize their hardware and software systems as efficiently as possible. Over the years, a field known as computer performance evaluation has arisen to address the problem of quantifying and predicting computer performance. Methods exist that can determine how efficiently a system's resources are being used. These can help track down the probable causes of performance problems

Uma abordagem de monitoração wireless em um ambiente de cluster com alta disponibilidade

Dissertação (mestrado) - Universidade Federal de Santa Catarina, Centro Tecnológico. Programa de Pós-Graduação em Ciência da Computação.O cenário que surge com a maior utilização dos sistemas computacionais de alto desempenho e mais recentemente com o advento das redes locais wireless tem requerido uma demanda cada vez maior por ferramentas e mecanismos para o controle e monitoração destes ambientes. Esse fato decorre, uma vez que a utilização destes sistemas computacionais em ambientes reais tem a cada dia nos indicado a necessidade do seu contínuo funcionamento. Desta forma, muitos serviços têm que estar disponíveis de forma ininterrupta. Possíveis falhas podem causar erros, fazendo com que o sistema apresente um defeito. Por esta razão, uma forma de redundância se faz necessária para evitar que tais defeitos acarretem prejuízos ao ambiente de alto desempenho

Dynamically reconfigurable architecture for embedded computer vision systems

The objective of this research work is to design, develop and implement a new architecture which integrates on the same chip all the processing levels of a complete Computer Vision system, so that the execution is efficient without compromising the power consumption while keeping a reduced cost. For this purpose, an analysis and classification of different mathematical operations and algorithms commonly used in Computer Vision are carried out, as well as a in-depth review of the image processing capabilities of current-generation hardware devices. This permits to determine the requirements and the key aspects for an efficient architecture. A representative set of algorithms is employed as benchmark to evaluate the proposed architecture, which is implemented on an FPGA-based system-on-chip. Finally, the prototype is compared to other related approaches in order to determine its advantages and weaknesses