Simplified state update calculation for fast and accurate digital emulation of CNN dynamics

Compared to other one-step integration methods, the 4th-order Runge-Kutta is much more accurate while still consisting in a rather reduced algorithmic structure. However, in terms of the computing power, it is more expensive than others. While the Forward Euler's method updates the state variable with a single evaluation of the derivative, 4th-order Runge-Kutta's method requires four. This is the reason why, when simulation speed is a central matter, e. g. in the digital emulation of CNN dynamics, the speed-accuracy trade-off is resolved in favour of the simpler, though less accurate, methods. A workaround for the computationally intensive calculation of the state variable update can be found for certain CNN models. If a FSR CNN model is employed, where the state variable is not allowed to go beyond the limits of the linear region of the cell output characteristic, the output can be identified with the state. In these conditions, and having linear templates, the update of the state variable can be computed, for a 4th-order Runge-Kutta's method, with a single function evaluation. It means that a digital emulation of the CNN dynamics following this method is as light-weighted as a Forward Euler's integrator, but much more accurate.Junta de Andalucía 2006-TIC-235

A számítási pontosság és robosztusság kérdésének elemzése analogikai CNN algoritmusok néhány osztályában = Analysis of computation accuracy and robustness in some classes of analogic CNN algorithms

A CNN tömbök analóg VLSI implementációi teraoperáció/s számítási teljesítményt adnak, pontosságuk viszont 6-7 bit. Komplex tér-idő dinamikával rendelkező rendszerek viselkedésének vizsgálatánál ez a pontosság nem elegendő. Ekkor előtérbe kerülnek az emulált digitális CNN-UM implementációk (ASIC vagy FPGA). - Elemeztük az emlős retina, az óceán áramlás és a taktilis nyomásérzékelő valamint a földrengés hullámok viselkedését. Összefüggéseket adtunk a számítási pontosság, az implementálható emulált digitális CNN cellaszám és a számítás sebessége között. - A vizsgálatok alapján az adott feladatosztályokra kijelölhető volt a minimális számítási pontosság igény. - Képmegjelenítőkön alkalmazható új al-pixel architektúrákat és a megjelenítendő kép fénysűrűség-eloszlását nagy térbeli felbontással figyelembe vevő ''image rendering'' algoritmusokat találtunk, amelyeknél - valós idejű alkalmazásoknál a számításigény miatt - fontos a gyors CNN transzformáció alkalmazása. - Kimutattuk, hogy a színi mérethatás szignifikáns, és a kis méretű színi stimulustól jellegzetes függést mutat, valamint javaslatot tettünk ennek modellezésére. - Kimutattuk, hogy a színmemóriából a megfigyelő által reprodukált színészlelet különbözik a közvetlenül megfigyelt színészlelettől, és számszerűsítettük ezeket a különbségeket. A színmemória-hatásokat - a nagy számításigény miatt - érdemes CNN-transzformációval modellezni. | Analog VLSI implementations of CNN arrays exhibit teraoperatio/s computing power but the accyracy of the computations are limited to 6-7 bits.In analysis of systems with complex spatio-temporal dynamics tis accuracy is not enough. Emulated digital CNN arrays are used in this case (ASIC or FPGA). - The vertabrate retina model, the ocean model, the tactile sensor model and the seismic wave model were analysed. Relationships were defined among the computing accuracy, the implementable number of emulated digital CNN cells and the speed of computation. - The minimal accuracy requirements were defined for the different problem classes. - New subpixel arrangements and color rendering methods for multi primary displays were developed. In real-time processing problems the huge computing power is an important issue and the CNN thechnology can be used here effectively. - The color size effect was analysed and a new model were developed. - The difference between the color coming from the long-term memory and the sensed color could be quantified. The color memory models need a large computing power and the CNN technology can be effective in this field too

Current-Mode Techniques for the Implementation of Continuous- and Discrete-Time Cellular Neural Networks

This paper presents a unified, comprehensive approach to the design of continuous-time (CT) and discrete-time (DT) cellular neural networks (CNN) using CMOS current-mode analog techniques. The net input signals are currents instead of voltages as presented in previous approaches, thus avoiding the need for current-to-voltage dedicated interfaces in image processing tasks with photosensor devices. Outputs may be either currents or voltages. Cell design relies on exploitation of current mirror properties for the efficient implementation of both linear and nonlinear analog operators. These cells are simpler and easier to design than those found in previously reported CT and DT-CNN devices. Basic design issues are covered, together with discussions on the influence of nonidealities and advanced circuit design issues as well as design for manufacturability considerations associated with statistical analysis. Three prototypes have been designed for l.6-pm n-well CMOS technologies. One is discrete-time and can be reconfigured via local logic for noise removal, feature extraction (borders and edges), shadow detection, hole filling, and connected component detection (CCD) on a rectangular grid with unity neighborhood radius. The other two prototypes are continuous-time and fixed template: one for CCD and other for noise removal. Experimental results are given illustrating performance of these prototypes

Payload-Byte: A Tool for Extracting and Labeling Packet Capture Files of Modern Network Intrusion Detection Datasets

Adapting modern approaches for network intrusion detection is becoming critical, given the rapid technological advancement and adversarial attack rates. Therefore, packet-based methods utilizing payload data are gaining much popularity due to their effectiveness in detecting certain attacks. However, packet-based approaches suffer from a lack of standardization, resulting in incomparability and reproducibility issues. Unlike flow-based datasets, no standard labeled dataset exists, forcing researchers to follow bespoke labeling pipelines for individual approaches. Without a standardized baseline, proposed approaches cannot be compared and evaluated with each other. One cannot gauge whether the proposed approach is a methodological advancement or is just being benefited from the proprietary interpretation of the dataset. Addressing comparability and reproducibility issues, we introduce Payload-Byte, an open-source tool for extracting and labeling network packets in this work. Payload-Byte utilizes metadata information and labels raw traffic captures of modern intrusion detection datasets in a generalized manner. Moreover, we transformed the labeled data into a byte-wise feature vector that can be utilized for training machine learning models. The whole cycle of processing and labeling is explicitly stated in this work. Furthermore, source code and processed data are made publicly available so that it may act as a standardized baseline for future research work. Lastly, we present a brief comparative analysis of machine learning models trained on packet-based and flow-based data

Stochastic and PWM coding for an efficient implementation of Cellular Neural Networks

This paper present the application of Pulse Stream Tech-niques (PSTs) to the hardware implementation of a Cellular Neural Network. The time differential equation of this networks suggests that the dynamic of one neuron status can be emulated by adding discretized packets of charge to a capacitor. This task can be carried out by driving a current source with a pulse stream signal

Latch-based RISC-V core with popcount instruction for CNN acceleration

Energy-efficiency is essential for vast majority of mobile and embedded battery-powered systems. Internet-of-Things paradigm combines requirements for high computational capabilities, extreme energy-efficiency and low-cost. Increasing manufacturing process variations pose formidable challenges for deep-submicron integrated circuit designs. The effects of variation are further exacerbated by lowered voltages in energy-efficient designs. Compared to traditional flip-flop-based design, latch-based design offers area, energy-efficiency and variation tolerance benefits at the cost of increased timing behavior complexity. A method for converting flip-flop-based processor core to latch-based core at register-transfer-level is presented in this work. Convolutional neural networks have enabled image recognition in the field of computer vision at unprecedented accuracy. Performance and memory requirements of canonical convolutional neural networks have been out of reach for low-cost IoT devices. In collaboration with Tampere University, a custom popcount instruction was added to the cores for accelerating IoT optimized vehicle classification convolutional neural network. This work compares simulation results from synthesized flip-flop-based and latch-based versions of a SCR1 RISC-V processor core and the effects of custom instruction for CNN acceleration. The latch core achieved roughly 50\% smaller energy per operation than the flip-flop core and 2.1x speedup was observed in the execution of the CNN when using the custom instruction