An Implementation of a Dual-Processor System on FPGA

In recent years, Field-Programmable Gate Arrays (FPGA) have evolved rapidly paving the way for a whole new range of computing paradigms. On the other hand, computer applications are evolving. There is a rising demand for a system that is general-purpose and yet has the processing abilities to accommodate current trends in application processing. This work proposes a design and implementation of a tightly-coupled FPGA-based dual-processor platform. We architect a platform that optimizes the utilization of FPGA resources and allows for the investigation of practical implementation issues such as cache design. The performance of the proposed prototype is then evaluated, as different configurations of a uniprocessor and a dual-processor system are studied and compared against each other and against published results for common industry-standard CPU platforms. The proposed implementation utilizes the Nios II 32-bit embedded soft-core processor architecture designed for the Altera Cyclone III family of FPGAs

Hardware/Software Co-design for Particle Swarm Optimization Algorithm

[[abstract]]This paper presents a hardware/software (HW/SW) co-design approach using SOPC technique and pipeline design method to improve the performance of particle swarm optimization (PSO) for embedded applications. Based on modular design architecture, a particle updating accelerator module via hardware implementation for updating velocity and position of particles and a fitness evaluation module implemented on a soft-cored processor for evaluating the objective functions are respectively designed and work closely together to accelerate the evolution process. Thanks to a flexible design, the proposed approach can tackle various optimization problems of embedded applications without the need for hardware redesign. To compensate the deficiency in generating truly random numbers by hardware implementation, a particle re-initialization scheme is also presented in this paper to further improve the execution performance of the PSO. Experiment results have demonstrated that the proposed HW/SW co-design approach to realize PSO is capable of achieving a high-quality solution effectively.[[conferencetype]]國際[[conferencedate]]20101010~20101013[[iscallforpapers]]Y[[conferencelocation]]Istanbul, Turke

Hardware/Software Co-design of Particle Filter and Its Application in Object Tracking

[[abstract]]This paper presents a hardware/software co-design method for particle filter based on System On Program Chip (SOPC) technique. Considering both the execution speed and design flexibility, we use a NIOS II processor to calculate weight for each particle and a hardware accelerator to update particles. As a result, execution efficiency of the proposed hardware/software co-design method of particle filter is significantly improved while maintaining design flexibility for various applications. To demonstrate the performance of the proposed approach, a real-time object tracking system is established and presented in this paper. Experimental results have demonstrated the proposed method have satisfactory results in real-time tracking of objects in video sequences.[[conferencetype]]國際[[conferencedate]]20110608~20110610[[conferencelocation]]Macao, Chin

Position and speed optimization of servo motor control through FPGA

We have put our model in this paper in which we will be controlling the speed and direction of the servomotor through FPGA. So, as to guarantee the precision from the check control procedure, we have made a project in which the document provides the control plane associated with servo motor depending on Altera DE1 board gentle primary processor as program controller. The system utilizes FPGA since the primary gadget, as well as within Quartus II 10.0 program atmosphere. The associated control components aremade to type a good executable control program in which speed and direction will be controlled the servo motor performance. The particular handle signs from your handle method are usually separated and amplified which results in the push to appreciate the particular handle with the servo motor. Based on the features associated with Altera, it is expounded through 2 facets of equipment’s hardware as well as a software program that supplies an answer for that style associated with the servo control system. This particular document utilizes the actual PID control formula to manage the actual common screening device to attain versatile as well as precise control reasons. The actual equipment execution from the PID control formula is put in place through FPGA; precise as well as effective control program is built to enhance the speed and performance of the servomotor through FPGA

Performance evaluation and limitations of a vision system on a reconfigurable/programmable chip

This paper presents a survey of the characteristics of a vision system implemented in a reconfigurable/programmable chip (FPGA). System limitations and performance have been evaluated in order to derive specifications and constraints for further vision system synthesis. The system hereby reported has a conventional architecture. It consists in a central microprocessor (CPU) and the necessary peripheral elements for data acquisition, data storage and communications. It has been designed to stand alone, but a link to the programming and debugging tools running in a digital host (PC) is provided. In order to alleviate the computational load of the central microprocessor, we have designed a visual co-processor in charge of the low-level image processing tasks. It operates autonomously, commanded by the CPU, as another system peripheral. The complete system, without the sensor, has been implemented in a single reconfigurable chip as a SOPC. The incorporation of a dedicated visual co-processor, with specific circuitry for low-level image processing acceleration, enhances the system throughput outperforming conventional processing schemes. However, time-multiplexing of the dedicated hardware remains a limiting factor for the achievable peak computing power. We have quantified this effect and sketched possible solutions, like replication of the specific image processing hardware. © J.UCS.This work has been partially funded by project FIT-330100-2005-162 of the Spanish Ministry of Industry, Tourism and Commerce. The work of F. J. Sánchez-Fernández is supported by a grant of the Spanish Ministry of Education and Science.Peer Reviewe

Performance evaluation and limitations of a vision system on a reconfigurable/programmable chip

This paper presents a survey of the characteristics of a vision system implemented in a reconfigurable/programmable chip (FPGA). System limitations and performance have been evaluated in order to derive specifications and constraints for further vision system synthesis. The system hereby reported has a conventional architecture. It consists in a central microprocessor (CPU) and the necessary peripheral elements for data acquisition, data storage and communications. It has been designed to stand alone, but a link to the programming and debugging tools running in a digital host (PC) is provided. In order to alleviate the computational load of the central microprocessor, we have designed a visual co-processor in charge of the low-level image processing tasks. It operates autonomously, commanded by the CPU, as another system peripheral. The complete system, without the sensor, has been implemented in a single reconfigurable chip as a SOPC. The incorporation of a dedicated visual co-processor, with specific circuitry for low-level image processing acceleration, enhances the system throughput outperforming conventional processing schemes. However, timemultiplexing of the dedicated hardware remains a limiting factor for the achievable peak computing power. We have quantified this effect and sketched possible solutions, like replication of the specific image processing hardware