3,261 research outputs found
Refinement Modal Logic
In this paper we present {\em refinement modal logic}. A refinement is like a
bisimulation, except that from the three relational requirements only `atoms'
and `back' need to be satisfied. Our logic contains a new operator 'all' in
addition to the standard modalities 'box' for each agent. The operator 'all'
acts as a quantifier over the set of all refinements of a given model. As a
variation on a bisimulation quantifier, this refinement operator or refinement
quantifier 'all' can be seen as quantifying over a variable not occurring in
the formula bound by it. The logic combines the simplicity of multi-agent modal
logic with some powers of monadic second-order quantification. We present a
sound and complete axiomatization of multi-agent refinement modal logic. We
also present an extension of the logic to the modal mu-calculus, and an
axiomatization for the single-agent version of this logic. Examples and
applications are also discussed: to software verification and design (the set
of agents can also be seen as a set of actions), and to dynamic epistemic
logic. We further give detailed results on the complexity of satisfiability,
and on succinctness
A formal model of asynchronous communication and its use in mechanically verifying a biphase mark protocol
In this paper we present a formal model of asynchronous communication as a function in the Boyer-Moore logic. The function transforms the signal stream generated by one processor into the signal stream consumed by an independently clocked processor. This transformation 'blurs' edges and 'dilates' time due to differences in the phases and rates of the two clocks and the communications delay. The model can be used quantitatively to derive concrete performance bounds on asynchronous communications at ISO protocol level 1 (physical level). We develop part of the reusable formal theory that permits the convenient application of the model. We use the theory to show that a biphase mark protocol can be used to send messages of arbitrary length between two asynchronous processors. We study two versions of the protocol, a conventional one which uses cells of size 32 cycles and an unconventional one which uses cells of size 18. We conjecture that the protocol can be proved to work under our model for smaller cell sizes and more divergent clock rates but the proofs would be harder
Digital Quantum Rabi and Dicke Models in Superconducting Circuits
We propose the analog-digital quantum simulation of the quantum Rabi and
Dicke models using circuit quantum electrodynamics (QED). We find that all
physical regimes, in particular those which are impossible to realize in
typical cavity QED setups, can be simulated via unitary decomposition into
digital steps. Furthermore, we show the emergence of the Dirac equation
dynamics from the quantum Rabi model when the mode frequency vanishes. Finally,
we analyze the feasibility of this proposal under realistic superconducting
circuit scenarios.Comment: 5 pages, 3 figures. Published in Scientific Report
Asynchronous Datapaths and the Design of an Asynchronous Adder
This paper presents a general method for designing delay insensitive datapath circuits. Its emphasis is on the formal derivation of a circuit from its specification. We discuss the properties required in a code that is used to transmit data asynchronously, and we introduce such a code. We introduce a general method (in the form of a theorem) for distributing the evaluation of a function over a number of concurrent cells. This method requires that the code be "distributive." We apply the method to the familiar example of a ripple-carry adder, and we give a CMOS implementation of the adder
Modular specifications in process algebra
In recent years a wide variety of process algebras has been proposed in the literature. Often these process algebras are closely related: they can be viewed as homomorphic images, submodels or restrictions of each other. The aim of this paper is to show how the semantical reality, consisting of a large number of closely related process algebras, can be reflected, and even used, on the level of algebraic specifications and in process verifications. This is done by means of the notion of a module. The simplest modules are building blocks of operators and axioms, each block describing a feature of concurrency in a certain semantical setting. These modules can then be combined by means of a union operator +, an export operator â–¡, allowing to forget some operators in a module, an operator H, changing semantics by taking homomorphic images, and an operator S which takes subalgebras. These operators enable us to combine modules in a subtle way, when the direct combination would be inconsistent. We show how auxiliary process algebra operators can be hidden when this is needed. Moreover it is demonstrated how new process combinators can be defined in terms of the more elementary ones in a clean way. As an illustration of our approach, a methodology is presented that can be used to specify FIFO-queues, and that facilitates verification of concurrent systems containing these queues
Kerdock Codes Determine Unitary 2-Designs
The non-linear binary Kerdock codes are known to be Gray images of certain
extended cyclic codes of length over . We show that
exponentiating these -valued codewords by produces stabilizer states, that are quantum states obtained using
only Clifford unitaries. These states are also the common eigenvectors of
commuting Hermitian matrices forming maximal commutative subgroups (MCS) of the
Pauli group. We use this quantum description to simplify the derivation of the
classical weight distribution of Kerdock codes. Next, we organize the
stabilizer states to form mutually unbiased bases and prove that
automorphisms of the Kerdock code permute their corresponding MCS, thereby
forming a subgroup of the Clifford group. When represented as symplectic
matrices, this subgroup is isomorphic to the projective special linear group
PSL(). We show that this automorphism group acts transitively on the Pauli
matrices, which implies that the ensemble is Pauli mixing and hence forms a
unitary -design. The Kerdock design described here was originally discovered
by Cleve et al. (arXiv:1501.04592), but the connection to classical codes is
new which simplifies its description and translation to circuits significantly.
Sampling from the design is straightforward, the translation to circuits uses
only Clifford gates, and the process does not require ancillary qubits.
Finally, we also develop algorithms for optimizing the synthesis of unitary
-designs on encoded qubits, i.e., to construct logical unitary -designs.
Software implementations are available at
https://github.com/nrenga/symplectic-arxiv18a, which we use to provide
empirical gate complexities for up to qubits.Comment: 16 pages double-column, 4 figures, and some circuits. Accepted to
2019 Intl. Symp. Inf. Theory (ISIT), and PDF of the 5-page ISIT version is
included in the arXiv packag
An Approximate Inner Bound to the QoS Aware Throughput Region of a Tree Network under IEEE 802.15.4 CSMA/CA and Application to Wireless Sensor Network Design
We consider a tree network spanning a set of source nodes that generate
measurement packets, a set of additional relay nodes that only forward packets
from the sources, and a data sink. We assume that the paths from the sources to
the sink have bounded hop count. We assume that the nodes use the IEEE 802.15.4
CSMA/CA for medium access control, and that there are no hidden terminals. In
this setting, starting with a set of simple fixed point equations, we derive
sufficient conditions for the tree network to approximately satisfy certain
given QoS targets such as end-to-end delivery probability and delay under a
given rate of generation of measurement packets at the sources (arrival rates
vector). The structures of our sufficient conditions provide insight on the
dependence of the network performance on the arrival rate vector, and the
topological properties of the network. Furthermore, for the special case of
equal arrival rates, default backoff parameters, and for a range of values of
target QoS, we show that among all path-length-bounded trees (spanning a given
set of sources and BS) that meet the sufficient conditions, a shortest path
tree achieves the maximum throughput
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