Modelling and Test Generation for Crosstalk Faults in DSM Chips

In the era of deep submicron technology (DSM), many System-on-Chip (SoC) applications require the components to be operating at high clock speeds. With the shrinking feature size and ever increasing clock frequencies, the DSM technology has led to a well-known problem of Signal Integrity (SI) more especially in the connecting layout design. The increasing aspect ratios of metal wires and also the ratio of coupling capacitance over substrate capacitance result in electrical coupling of interconnects which leads to crosstalk problems. In this thesis, first the work carried out to model the crosstalk behaviour between aggressor and victim by considering the distributed RLGC parameters of interconnect and the coupling capacitance and mutual conductance between the two nets is presented. The proposed model also considers the RC linear models of the CMOS drivers and receivers. The behaviour of crosstalk in case of under etching problem has been studied and modelled by distributing and approximating the defect behaviour throughout the nets. Next, the proposed model has also been extended to model the behaviour of crosstalk in case of one victim is influenced by several aggressors by considering all aggressors have similar effect (worst-case) on victim. In all the above cases simulation experiments were also carried out and compared with well-known circuit simulation tool PSPICE. It has been proved that the generated crosstalk model is faster and the results generated are within 10% of error margin compared to latter simulation tool. Because of the accuracy and speed of the proposed model, the model is very useful for both SoC designers and test engineers to analyse the crosstalk behaviour. Each manufactured device needs to be tested thoroughly to ensure the functionality before its delivery. The test pattern generation for crosstalk faults is also necessary to test the corresponding crosstalk faults. In this thesis, the well-known PODEM algorithm for stuck-at faults is extended to generate the test patterns for crosstalk faults between single aggressor and single victim. To apply modified PODEM for crosstalk faults, the transition behaviour has been divided into two logic parts as before transition and after transition. After finding individually required test patterns for before transition and after transition, the generated logic vectors are appended to create transition test patterns for crosstalk faults. The developed algorithm is also applied for a few ISCAS 85 benchmark circuits and the fault coverage is found excellent in most circuits. With the incorporation of proposed algorithm into the ATPG tools, the efficiency of testing will be improved by generating the test patterns for crosstalk faults besides for the conventional stuck-at faults. In generating test patterns for crosstalk faults on single victim due to multiple aggressors, the modified PODEM algorithm is found to be more time consuming. The search capability of Genetic Algorithms in finding the required combination of several input factors for any optimized problem fascinated to apply GA for generating test patterns as generating the test pattern is also similar to finding the required vector out of several input transitions. Initially the GA is applied for generating test patterns for stuck-at faults and compared the results with PODEM algorithm. As the fault coverage is almost similar to the deterministic algorithm PODEM, the GA developed for stuck-at faults is extended to find test patterns for crosstalk faults between single aggressor and single victim. The elitist GA is also applied for a few ISCAS 85 benchmark circuits. Later the algorithm is extended to generate test patterns for worst-case crosstalk faults. It has been proved that elitist GA developed in this thesis is also very useful in generating test patterns for crosstalk faults especially for multiple aggressor and single victim crosstalk faults

The characterisation, modelling and detection of series arc faults in aircraft electrical power distribution systems featuring solid state power controllers (SSPCs)

Electrical power demand in aircraft has grown significantly over the last century, and this trend continues with the More Electric Aircraft (MEA) and All Electric Aircraft (AEA) concepts. Higher voltages such as 270VDC are required to deliver additional power to loads and to optimise aircraft mass. Increased voltages inflict more stress on the Electrical Wiring Interconnect System (EWIS) and increase the impact of series arc faults caused by wiring defects. Solid State Power Controllers (SSPCs) are used to provide fast protection in high voltage distribution systems. The aim of this work is the characterisation, modelling, simulation and detection of series arc faults in 28VDC and 270VDC electrical power distribution systems featuring SSPCs. The majority of passive detection schemes in the literature were designed based on empirical data rather than well characterised electric arc parameters, and thus nuisance trips are unavoidable. To address this series arc faults in 28VDC and 270VDC solid state power distribution systems were characterised using the SAE5692 "Loose terminal" method [8], and it was found that 270VDC arc faults cause a minimal ~5.6% reduction in loop current and load voltage compared with ~54% in 28VDC systems. SSPC output voltage transients caused by series arcs were found to be limited by the presence of SSPC snubbers. Increasing the system loop inductance was found to improve series arc stability resulting in fewer arc quench events. Increasing the capacitive load reduces arc stability and causes arcs to quench more readily thus simplifying detection. These results were later used to experimentally validate a novel series arc fault SPICE model based on the static Nottingham V-I model [9] and wider solid state electrical system model. The arc current and SSPC output voltage results were also used to create a prototype passive series arc fault detection system, which has been demonstrated to SAE5692 under laboratory conditions [8]. A novel multilayer PCB current sensor was developed and experimentally validated for this prototype. To further reduce nuisance trips an innovative active arc fault perturbation scheme was simulated and experimentally demonstrated using SSPC modulation to stimulate and detect arc quench. Another novel complementary series arc fault prevention / confirmation scheme was simulated and experimentally validated using SSPC leakage currents. To minimise nuisance trips due to manufacturing and installation errors a unique Built-In Test (BIT) scheme was also developed and experimentally validated using the SSPC to create artificial current and voltage stimuli

Design and debugging of multi-step analog to digital converters

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has forced the A/D converter interface to reside on the same silicon in complex mixed-signal ICs containing mostly digital blocks for DSP and control. However, specifications of the converters in various applications emphasize high dynamic range and low spurious spectral performance. It is nontrivial to achieve this level of linearity in a monolithic environment where post-fabrication component trimming or calibration is cumbersome to implement for certain applications or/and for cost and manufacturability reasons. Additionally, as CMOS integrated circuits are accomplishing unprecedented integration levels, potential problems associated with device scaling – the short-channel effects – are also looming large as technology strides into the deep-submicron regime. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. Practical realizations show the trend that to a first order, converter power is directly proportional to sampling rate. However, power dissipation required becomes nonlinear as the speed capabilities of a process technology are pushed to the limit. Pipeline and two-step/multi-step converters tend to be the most efficient at achieving a given resolution and sampling rate specification. This thesis is in a sense unique work as it covers the whole spectrum of design, test, debugging and calibration of multi-step A/D converters; it incorporates development of circuit techniques and algorithms to enhance the resolution and attainable sample rate of an A/D converter and to enhance testing and debugging potential to detect errors dynamically, to isolate and confine faults, and to recover and compensate for the errors continuously. The power proficiency for high resolution of multi-step converter by combining parallelism and calibration and exploiting low-voltage circuit techniques is demonstrated with a 1.8 V, 12-bit, 80 MS/s, 100 mW analog to-digital converter fabricated in five-metal layers 0.18-µm CMOS process. Lower power supply voltages significantly reduce noise margins and increase variations in process, device and design parameters. Consequently, it is steadily more difficult to control the fabrication process precisely enough to maintain uniformity. Microscopic particles present in the manufacturing environment and slight variations in the parameters of manufacturing steps can all lead to the geometrical and electrical properties of an IC to deviate from those generated at the end of the design process. Those defects can cause various types of malfunctioning, depending on the IC topology and the nature of the defect. To relive the burden placed on IC design and manufacturing originated with ever-increasing costs associated with testing and debugging of complex mixed-signal electronic systems, several circuit techniques and algorithms are developed and incorporated in proposed ATPG, DfT and BIST methodologies. Process variation cannot be solved by improving manufacturing tolerances; variability must be reduced by new device technology or managed by design in order for scaling to continue. Similarly, within-die performance variation also imposes new challenges for test methods. With the use of dedicated sensors, which exploit knowledge of the circuit structure and the specific defect mechanisms, the method described in this thesis facilitates early and fast identification of excessive process parameter variation effects. The expectation-maximization algorithm makes the estimation problem more tractable and also yields good estimates of the parameters for small sample sizes. To allow the test guidance with the information obtained through monitoring process variations implemented adjusted support vector machine classifier simultaneously minimize the empirical classification error and maximize the geometric margin. On a positive note, the use of digital enhancing calibration techniques reduces the need for expensive technologies with special fabrication steps. Indeed, the extra cost of digital processing is normally affordable as the use of submicron mixed signal technologies allows for efficient usage of silicon area even for relatively complex algorithms. Employed adaptive filtering algorithm for error estimation offers the small number of operations per iteration and does not require correlation function calculation nor matrix inversions. The presented foreground calibration algorithm does not need any dedicated test signal and does not require a part of the conversion time. It works continuously and with every signal applied to the A/D converter. The feasibility of the method for on-line and off-line debugging and calibration has been verified by experimental measurements from the silicon prototype fabricated in standard single poly, six metal 0.09-µm CMOS process

Analysis of performance of SiC bipolar semiconductor devices for grid-level converters

Recent commercialization of SiC bipolar devices, including SiC BJT, SiC MPS diode and SiC PiN diodes have enabled potential candidates to replace their SiC unipolar counterparts. However, the prospects of 4H-SiC power bipolar devices still need further investigation. This thesis compares the static and dynamic performance and reliability for the commercial SiC bipolar devices including SiC BJT, SiC MPS diode and SiC PiN diode and their similarly rated Silicon counterparts mainly by means of experimental measurements.Through comprehensive double-pulse measurements, the turn-on and turn-off transition in Silicon BJT is seen to be much slower than that of the SiC BJT while the transient time will increase with temperature and decreases with collector currents. The common-emitter current gain (β) of SiC BJT is also found to be much higher than its Silicon counterpart. Significant turn-off delay is observed in single Si BJT which becomes worse when in parallel connection as it aggravates the current mismatch across the two devices, while this delay is almost non-existent in SiC devices. The current collapse seen in single SiC BJT is mitigated by parallel connection. These are dependant on temperature and base resistance, especially in the case of Silicon BJT. The static performance of power Silicon and SiC BJT has also been evaluated. It has been found that the higher base-emitter junction voltage of SiC BJTs enables quasi-saturation mode of operation with low on-resistance, which is also the case for Silicon BJTs only at high base currents. In terms of DC gain measured under steady state operation, the observed negative temperature coefficient (NTC) of β in SiC BJTs and the positive coefficient (PTC) in Silicon BJTs can make the β of SiC BJT lower than that in Silicon at high temperatures. It has been found that parallel connection promotes both the on-state conductivity and current gain in Silicon BJTs and conductivity in SiC BJTs.The characterization of power diodes reveals that the superior switching performance of the SiC MPS & JBS diode when compared with the Si PiN diode is due to the absence of the stored charge. This also leads to the larger on-state voltage in both SiC diodes and becomes worse at high currents under high temperatures. Through comprehensive Unclamped Inductive Switching (UIS) measurements, it is seen that the avalanche ruggedness of SiC MPS & JBS diodes outperform that of the closely rated Silicon PiN diode taking advantage of the wide-bandgap properties of SiC. Higher critical avalanche energy and thus better avalanche ruggedness can also be observed in SiC JBS diode compared with the SiC MPS diode. SiC MPS diodes can compete with Si PiN diodes in terms of the surge current limits, while the SiC JBS diode failed under a lower electrothermal stress. This is observed by the dramatic increase in its reverse leakage current at lower voltages.The 15 kV SiC PiN diodes feature smaller device dimensions, less reverse recovery charge and less on-resistance when compared to the 15 kV Silicon PiN diodes. Nevertheless, when evaluating its long-term reliability by using the aggravated power cycling configuration, the high junction temperature together with the dislocation defects in the SiC PiN diode accelerate its degradation. Such degradations are not observed in Silicon PiN diodes for the same junction temperature and high-temperature stress periods

Design Space Exploration and Resource Management of Multi/Many-Core Systems

The increasing demand of processing a higher number of applications and related data on computing platforms has resulted in reliance on multi-/many-core chips as they facilitate parallel processing. However, there is a desire for these platforms to be energy-efficient and reliable, and they need to perform secure computations for the interest of the whole community. This book provides perspectives on the aforementioned aspects from leading researchers in terms of state-of-the-art contributions and upcoming trends

State-of-the-Art Sensors Technology in Spain 2015: Volume 1

This book provides a comprehensive overview of state-of-the-art sensors technology in specific leading areas. Industrial researchers, engineers and professionals can find information on the most advanced technologies and developments, together with data processing. Further research covers specific devices and technologies that capture and distribute data to be processed by applying dedicated techniques or procedures, which is where sensors play the most important role. The book provides insights and solutions for different problems covering a broad spectrum of possibilities, thanks to a set of applications and solutions based on sensory technologies. Topics include: • Signal analysis for spectral power • 3D precise measurements • Electromagnetic propagation • Drugs detection • e-health environments based on social sensor networks • Robots in wireless environments, navigation, teleoperation, object grasping, demining • Wireless sensor networks • Industrial IoT • Insights in smart cities • Voice recognition • FPGA interfaces • Flight mill device for measurements on insects • Optical systems: UV, LEDs, lasers, fiber optics • Machine vision • Power dissipation • Liquid level in fuel tanks • Parabolic solar tracker • Force sensors • Control for a twin roto

Magnetic Tape Recording for the Eighties

The practical and theoretical aspects of state-of-the-art magnetic tape recording technology are reviewed. Topics covered include the following: (1) analog and digital magnetic tape recording, (2) tape and head wear, (3) wear testing, (4) magnetic tape certification, (5) care, handling, and management of magnetic tape, (6) cleaning, packing, and winding of magnetic tape, (7) tape reels, bands, and packaging, (8) coding techniques for high-density digital recording, and (9) tradeoffs of coding techniques