Parallel algorithms and architectures for low power video decoding

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2010.Cataloged from PDF version of thesis.Includes bibliographical references (p. 197-204).Parallelism coupled with voltage scaling is an effective approach to achieve high processing performance with low power consumption. This thesis presents parallel architectures and algorithms designed to deliver the power and performance required for current and next generation video coding. Coding efficiency, area cost and scalability are also addressed. First, a low power video decoder is presented for the current state-of-the-art video coding standard H.264/AVC. Parallel architectures are used along with voltage scaling to deliver high definition (HD) decoding at low power levels. Additional architectural optimizations such as reducing memory accesses and multiple frequency/voltage domains are also described. An H.264/AVC Baseline decoder test chip was fabricated in 65-nm CMOS. It can operate at 0.7 V for HD (720p, 30 fps) video decoding and with a measured power of 1.8 mW. The highly scalable decoder can tradeoff power and performance across >100x range. Second, this thesis demonstrates how serial algorithms, such as Context-based Adaptive Binary Arithmetic Coding (CABAC), can be redesigned for parallel architectures to enable high throughput with low coding efficiency cost. A parallel algorithm called the Massively Parallel CABAC (MP-CABAC) is presented that uses syntax element partitions and interleaved entropy slices to achieve better throughput-coding efficiency and throughput-area tradeoffs than H.264/AVC. The parallel algorithm also improves scalability by providing a third dimension to tradeoff coding efficiency for power and performance. Finally, joint algorithm-architecture optimizations are used to increase performance and reduce area with almost no coding penalty. The MP-CABAC is mapped to a highly parallel architecture with 80 parallel engines, which together delivers >10x higher throughput than existing H.264/AVC CABAC implementations. A MP-CABAC test chip was fabricated in 65-nm CMOS to demonstrate the power-performance-coding efficiency tradeoff.by Vivienne. Sze.Ph.D

Quality-Oriented Mobility Management for Multimedia Content Delivery to Mobile Users

The heterogeneous wireless networking environment determined by the latest developments in wireless access technologies promises a high level of communication resources for mobile computational devices. Although the communication resources provided, especially referring to bandwidth, enable multimedia streaming to mobile users, maintaining a high user perceived quality is still a challenging task. The main factors which affect quality in multimedia streaming over wireless networks are mainly the error-prone nature of the wireless channels and the user mobility. These factors determine a high level of dynamics of wireless communication resources, namely variations in throughput and packet loss as well as network availability and delays in delivering the data packets. Under these conditions maintaining a high level of quality, as perceived by the user, requires a quality oriented mobility management scheme. Consequently we propose the Smooth Adaptive Soft-Handover Algorithm, a novel quality oriented handover management scheme which unlike other similar solutions, smoothly transfer the data traffic from one network to another using multiple simultaneous connections. To estimate the capacity of each connection the novel Quality of Multimedia Streaming (QMS) metric is proposed. The QMS metric aims at offering maximum flexibility and efficiency allowing the applications to fine tune the behavior of the handover algorithm. The current simulation-based performance evaluation clearly shows the better performance of the proposed Smooth Adaptive Soft-Handover Algorithm as compared with other handover solutions. The evaluation was performed in various scenarios including multiple mobile hosts performing handover simultaneously, wireless networks with variable overlapping areas, and various network congestion levels

Estudio de Arquitecturas VLSI de la etapa de predicción de la compensación de movimiento, para compresión de imágenes y video con Algoritmos full-search. Aplicación al estándar H.264/AVC

En esta tesis doctoral se presenta el diseño y realización de arquitecturas VLSI de estimación de movimiento, en sus versiones de pixeles enteros y fraccionarios, para la etapa de predicción de la compensación de movimiento del estándar de codificación de video H.264/AVC. Las arquitecturas propuestas son estructuras de procesamiento pipeline-paralelas con alta eficiencia en su data_path y una administración optima de la memoria. Utilizando el algoritmo full-search block matching, los diseños cumplen los requerimientos de tamaño de bloque variable y resolución de ¼ de píxel del estándar con máxima calidad. Los estimadores de movimiento combinan las características de las arquitecturas consideradas en el estado del arte junto con la aplicación de nuevos esquemas y algoritmos hardware, en el proceso de codificación del componente luma de la señal de video. Diseñadas como coprocesadores de aceleración hardware para procesadores de 32 bits, las arquitecturas que se presentan han sido simuladas y sintetizadas para FPGA Virtex-4 de Xilinx, utilizando el lenguaje de descripción de hardware VHDL.Mora Campos, A. (2008). Estudio de Arquitecturas VLSI de la etapa de predicción de la compensación de movimiento, para compresión de imágenes y video con Algoritmos full-search. Aplicación al estándar H.264/AVC [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/3446Palanci