Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

An Experimental Study of Reduced-Voltage Operation in Modern FPGAs for Neural Network Acceleration

We empirically evaluate an undervolting technique, i.e., underscaling the circuit supply voltage below the nominal level, to improve the power-efficiency of Convolutional Neural Network (CNN) accelerators mapped to Field Programmable Gate Arrays (FPGAs). Undervolting below a safe voltage level can lead to timing faults due to excessive circuit latency increase. We evaluate the reliability-power trade-off for such accelerators. Specifically, we experimentally study the reduced-voltage operation of multiple components of real FPGAs, characterize the corresponding reliability behavior of CNN accelerators, propose techniques to minimize the drawbacks of reduced-voltage operation, and combine undervolting with architectural CNN optimization techniques, i.e., quantization and pruning. We investigate the effect of environmental temperature on the reliability-power trade-off of such accelerators. We perform experiments on three identical samples of modern Xilinx ZCU102 FPGA platforms with five state-of-the-art image classification CNN benchmarks. This approach allows us to study the effects of our undervolting technique for both software and hardware variability. We achieve more than 3X power-efficiency (GOPs/W) gain via undervolting. 2.6X of this gain is the result of eliminating the voltage guardband region, i.e., the safe voltage region below the nominal level that is set by FPGA vendor to ensure correct functionality in worst-case environmental and circuit conditions. 43% of the power-efficiency gain is due to further undervolting below the guardband, which comes at the cost of accuracy loss in the CNN accelerator. We evaluate an effective frequency underscaling technique that prevents this accuracy loss, and find that it reduces the power-efficiency gain from 43% to 25%.Comment: To appear at the DSN 2020 conferenc

Accounting for outliers and calendar effects in surrogate simulations of stock return sequences

Surrogate Data Analysis (SDA) is a statistical hypothesis testing framework for the determination of weak chaos in time series dynamics. Existing SDA procedures do not account properly for the rich structures observed in stock return sequences, attributed to the presence of heteroscedasticity, seasonal effects and outliers. In this paper we suggest a modification of the SDA framework, based on the robust estimation of location and scale parameters of mean-stationary time series and a probabilistic framework which deals with outliers. A demonstration on the NASDAQ Composite index daily returns shows that the proposed approach produces surrogates that faithfully reproduce the structure of the original series while being manifestations of linear-random dynamics.Comment: 21 pages, 7 figure

Combining Photometry From Kepler and TESS to Improve Short-Period Exoplanet Characterization

Planets emit thermal radiation and reflect incident light that they recieve from their host stars. As a planet orbits it's host star the photometric variations associated with these two effects produce very similar phase curves. If observed through only a single bandpass this leads to a degeneracy between certain planetary parameters that hinder the precise characterization of such planets. However, observing the same planet through two different bandpasses gives one much more information about the planet. Here, we develop a Bayesian methodology for combining photometry from both \emph{Kepler} and the Transiting Exoplanet Survey Satellite (TESS). In addition, we demonstrate via simulations that one can disentangle the reflected and thermally emitted light from the atmosphere of a hot-Jupiter as well as more precisely constrain both the geometric albedo and dayside temperature of the planet. This methodology can further be employed using various combinations of photometry from the James Webb Space Telescope (JWST), the Characterizing ExOplanet Satellite (CHEOPS), or the PLATO mission.Comment: Submitted to PAS

Characterization of Vehicle Behavior with Information Theory

This work proposes the use of Information Theory for the characterization of vehicles behavior through their velocities. Three public data sets were used: i.Mobile Century data set collected on Highway I-880, near Union City, California; ii.Borl\"ange GPS data set collected in the Swedish city of Borl\"ange; and iii.Beijing taxicabs data set collected in Beijing, China, where each vehicle speed is stored as a time series. The Bandt-Pompe methodology combined with the Complexity-Entropy plane were used to identify different regimes and behaviors. The global velocity is compatible with a correlated noise with f^{-k} Power Spectrum with k >= 0. With this we identify traffic behaviors as, for instance, random velocities (k aprox. 0) when there is congestion, and more correlated velocities (k aprox. 3) in the presence of free traffic flow