1,822 research outputs found

    Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey

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    Automatic Tuning of Silicon Photonics Millimeter-Wave Transceivers Building Blocks

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    Today, continuously growing wireless traffic have guided the progress in the wireless communication systems. Now, evolution towards next generation (5G) wireless communication systems are actively researched to accommodate expanding future data traffic. As one of the most promising candidates, integrating photonic devices in to the existing wireless system is considered to improve the performance of the systems. Emerging silicon photonic integrated circuits lead this integration more practically, and open new possibilities to the future communication systems. In this dissertation, the development of the electrical wireless communication systems are briefly explained. Also, development of the microwave photonics and silicon photonics are described to understand the possibility of the hybrid SiP integrated wireless communication systems. A limitation of the current electrical wireless systems are addressed, and hybrid integrated mm-wave silicon photonic receiver, and silicon photonic beamforming transmitter are proposed and analyzed in system level. In the proposed mm-wave silicon photonic receiver has 4th order pole-zero silicon photonic filter in the system. Photonic devices are vulnerable to the process and temperature variations. It requires manual calibration, which is expensive, time consuming, and prone to human errors. Therefore, precise automatic calibration solution with modified silicon photonic filter structure is proposed and demonstrated. This dissertation demonstrates fully automatic tuning of silicon photonic all-pass filter (APF)-based pole/zero filters using a monitor-based tuning method that calibrates the initial response by controlling each pole and zero individually via micro-heaters. The proposed tuning approach calibrates severely degraded initial responses to the designed elliptic filter shapes and allows for automatic bandwidth and center frequency reconfiguration of these filters. This algorithm is demonstrated on 2nd- and 4th-order filters fabricated in a standard silicon photonics foundry process. After the initial calibration, only 300ms is required to reconfigure a filter to a different center frequency. Thermal crosstalk between the micro-heaters is investigated, with substrate thinning demonstrated to suppress this effect and reduce filter calibration to less than half of the original thick substrate times. This fully automatic tuning approach opens the possibility of employing silicon photonic filters in real communication systems. Also, in the proposed beamforming transmitter, true-time delay ring resonator based 1x4 beamforming network is imbedded. A proposed monitor-based tuning method compensates fabrication variations and thermal crosstalk by controlling micro-heaters individually using electrical monitors. The proposed tuning approach successfully demonstrated calibration of OBFN from severely degraded initial responses to well-defined group delay response required for the targeted radiating angle with a range of 60◦ (-30◦ to 30◦ ) in a linear beamforming antenna array. This algorithm is demonstrated on OBFN fabricated in a standard silicon photonics foundry process. The calibrated OBFN operates at 30GHz and provide 2GHz bandwidth. This fully automatic tuning approach opens the possibility of employing silicon OBFN in real wideband mm-wave wireless communication systems by providing robust operating solutions. All the proposed photonic circuits are implemented using the standard silicon photonic technologies, and resulted in several publications in IEEE/OSA Journals and Conferences

    Circuit design and analysis for on-FPGA communication systems

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    On-chip communication system has emerged as a prominently important subject in Very-Large- Scale-Integration (VLSI) design, as the trend of technology scaling favours logics more than interconnects. Interconnects often dictates the system performance, and, therefore, research for new methodologies and system architectures that deliver high-performance communication services across the chip is mandatory. The interconnect challenge is exacerbated in Field-Programmable Gate Array (FPGA), as a type of ASIC where the hardware can be programmed post-fabrication. Communication across an FPGA will be deteriorating as a result of interconnect scaling. The programmable fabrics, switches and the specific routing architecture also introduce additional latency and bandwidth degradation further hindering intra-chip communication performance. Past research efforts mainly focused on optimizing logic elements and functional units in FPGAs. Communication with programmable interconnect received little attention and is inadequately understood. This thesis is among the first to research on-chip communication systems that are built on top of programmable fabrics and proposes methodologies to maximize the interconnect throughput performance. There are three major contributions in this thesis: (i) an analysis of on-chip interconnect fringing, which degrades the bandwidth of communication channels due to routing congestions in reconfigurable architectures; (ii) a new analogue wave signalling scheme that significantly improves the interconnect throughput by exploiting the fundamental electrical characteristics of the reconfigurable interconnect structures. This new scheme can potentially mitigate the interconnect scaling challenges. (iii) a novel Dynamic Programming (DP)-network to provide adaptive routing in network-on-chip (NoC) systems. The DP-network architecture performs runtime optimization for route planning and dynamic routing which, effectively utilizes the in-silicon bandwidth. This thesis explores a new horizon in reconfigurable system design, in which new methodologies and concepts are proposed to enhance the on-FPGA communication throughput performance that is of vital importance in new technology processes

    A Programmable Display-Layer Architecture for Virtual-Reality Applications

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    Two important technical objectives of virtual-reality systems are to provide compelling visuals and effective 3D user interaction. In this respect, modern virtual reality system architectures suffer from a number of short-comings. The reduction of end-to-end latency, crosstalk and judder are especially difficult challenges, each of which negatively affects visual quality or user interaction. In order to provide higher quality visuals, complex scenes consisting of large models are often used. Rendering such a complex scene is a time-consuming process resulting in high end-to-end latency, thereby hampering user interaction. Classic virtual-reality architectures can not adequately address these challenges due to their inherent design principles. In particular, the tight coupling between input devices, the rendering loop and the display system inhibits these systems from addressing all the aforementioned challenges simultaneously. In this thesis, a virtual-reality architecture design is introduced that is based on the addition of a new logical layer: the Programmable Display Layer (PDL). The governing idea is that an extra layer is inserted between the rendering system and the display. In this way, the display can be updated at a fast rate and in a custom manner independent of the other components in the architecture, including the rendering system. To generate intermediate display updates at a fast rate, the PDL performs per-pixel depth-image warping by utilizing the application data. Image warping is the process of computing a new image by transforming individual depth-pixels from a closely matching previous image to their updated locations. The PDL architecture can be used for a range of algorithms and to solve problems that are not easily solved using classic architectures. In particular, techniques to reduce crosstalk, judder and latency are examined using algorithms implemented on top of the PDL. Concerning user interaction techniques, several six-degrees-of-freedom input methods exists, of which optical tracking is a popular option. However, optical tracking methods also introduce several constraints that depend on the camera setup, such as line-of-sight requirements, the volume of the interaction space and the achieved tracking accuracy. These constraints generally cause a decline in the effectiveness of user interaction. To investigate the effectiveness of optical tracking methods, an optical tracker simulation framework has been developed, including a novel optical tracker to test this framework. In this way, different optical tracking algorithms can be simulated and quantitatively evaluated under a wide range of conditions. A common approach in virtual reality is to implement an algorithm and then to evaluate the efficacy of that algorithm by either subjective, qualitative metrics or quantitative user experiments, after which an updated version of the algorithm may be implemented and the cycle repeated. A different approach is followed here. Throughout this thesis, an attempt is made to automatically detect and quantify errors using completely objective and automated quantitative methods and to subsequently attempt to resolve these errors dynamically
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