1,240 research outputs found
Mapping unstructured grid problems to the connection machine
We present a highly parallel graph mapping technique that enables one to solve unstructured grid problems on massively parallel computers. Many implicit and explicit methods for solving discretizated partial differential equations require each point in the discretization to exchange data with its neighboring points every time step or iteration. The time spent communicating can limit the high performance promised by massively parallel computing. To eliminate this bottleneck, we map the graph of the irregular problem to the graph representing the interconnection topology of the computer such that the sum of the distances that the messages travel is minimized. We show that, in comparison to a naive assignment of processors, our heuristic mapping algorithm significantly reduces the communication time on the Connection Machine, CM-2
Mapping and FPGA global routing using Mean Field Annealing
Ankara : Department of Computer Engineering and Information Science and Institute of Engineering and Science, Bilkent University, 1994.Thesis (Master's) -- -Bilkent University, 1994.Includes bibliographical references leaves 71-73Haritaoğlu, İsmailM.S
Recent Advances in Graph Partitioning
We survey recent trends in practical algorithms for balanced graph
partitioning together with applications and future research directions
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An Interconnection Network Topology Generation Scheme for Multicore Systems
Multi-Processor System on Chip (MPSoC) consisting of multiple processing cores connected via a Network on Chip (NoC) has gained prominence over the last decade. Most common way of mapping applications to MPSoCs is by dividing the application into small tasks and representing them in the form of a task graph where the edges connecting the tasks represent the inter task communication. Task scheduling involves mapping task to processor cores so as to meet a specified deadline for the application/task graph. With increase in system complexity and application parallelism, task communication times are tending towards task execution times. Hence the NoC which forms the communication backbone for the cores plays a critical role in meeting the deadlines. In this thesis we present an approach to synthesize a minimal network connecting a set of cores in a MPSoC in the presence of deadlines. Given a task graph and a corresponding task to processor schedule, we have developed a partitioning methodology to generate an efficient interconnection network for the cores. We adopt a 2-phase design flow where we synthesize the network in first phase and in second phase we perform statistical analysis of the network thus generated. We compare our model with a simulated annealing based scheme, a static graph based greedy scheme and the standard mesh topology. The proposed solution offers significant area and performance benefits over the alternate solutions compared in this work
Parallel mapping and circuit partitioning heuristics based on mean field annealing
Ankara : Department of Computer Engineering and Information Science and the Institute of Engineering and Science of Bilkent University, 1992.Thesis (Master's) -- Bilkent University, 1992.Includes bibliographical references.Moan Field Annealinp; (MFA) aJgoritlim, receñí,ly proposc'd for solving com
binatorial optimization problems, combines the characteristics of nenral networks
and simulated annealing. In this thesis, MFA is formulated for tlie
mapping i)roblcm and the circuit partitioning problem. EHicient implementation
schemes, which decrease the complexity of the proposed algorithms by
asymptotical factors, are also given. Perlormances of the proposed MFA algorithms
are evaluated in comparison with two well-known heuristics: simulated
annealing and Kernighan-Lin. Results of the experiments indicate that MFA
can be used as an alternative heuristic for the mapping problem and the circuit
partitioning problem. Inherent parallelism of the MFA is exploited by
designing efficient parallel algorithms for the proposed MFA heuristics. Parallel
MFA algorithms proposed for solving the circuit partitioning problem are
implemented on an iPS(J/2’ hypercube multicompute.r. Experimental results
show that the proposed heuristics can be efficiently parallelized, which is crucial
for algorithms that solve such computationally hard problems.Bultan, TevfikM.S
Parallel and Distributed Computing
The 14 chapters presented in this book cover a wide variety of representative works ranging from hardware design to application development. Particularly, the topics that are addressed are programmable and reconfigurable devices and systems, dependability of GPUs (General Purpose Units), network topologies, cache coherence protocols, resource allocation, scheduling algorithms, peertopeer networks, largescale network simulation, and parallel routines and algorithms. In this way, the articles included in this book constitute an excellent reference for engineers and researchers who have particular interests in each of these topics in parallel and distributed computing
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