On the Verification of a WiMax Design Using Symbolic Simulation

In top-down multi-level design methodologies, design descriptions at higher levels of abstraction are incrementally refined to the final realizations. Simulation based techniques have traditionally been used to verify that such model refinements do not change the design functionality. Unfortunately, with computer simulations it is not possible to completely check that a design transformation is correct in a reasonable amount of time, as the number of test patterns required to do so increase exponentially with the number of system state variables. In this paper, we propose a methodology for the verification of conformance of models generated at higher levels of abstraction in the design process to the design specifications. We model the system behavior using sequence of recurrence equations. We then use symbolic simulation together with equivalence checking and property checking techniques for design verification. Using our proposed method, we have verified the equivalence of three WiMax system models at different levels of design abstraction, and the correctness of various system properties on those models. Our symbolic modeling and verification experiments show that the proposed verification methodology provides performance advantage over its numerical counterpart.Comment: In Proceedings SCSS 2012, arXiv:1307.802

The Challenge of Hardware Synthesis from C-like Languages

Many techniques for synthesizing digital hardware from C-like languages have been proposed, but none have emerged as successful as Verilog or VHDL for register-transfer-level design. Familiarity is the main reason C-like languages have been proposed for hardware synthesis. Synthesize hardware from C, proponents claim, and a C programmer can be turned into a hardware designer. Another common motivation is hardware/software codesign: today's systems usually contain a mix of hardware and software, and it is often unclear initially which portions to implement in hardware. Here, using a single language should simplify the migration task. The paper surveys several C-like hardware synthesis languages and looks at two of the fundamental challenges, concurrency and timing control

User-centred design of flexible hypermedia for a mobile guide: Reflections on the hyperaudio experience

A user-centred design approach involves end-users from the very beginning. Considering users at the early stages compels designers to think in terms of utility and usability and helps develop the system on what is actually needed. This paper discusses the case of HyperAudio, a context-sensitive adaptive and mobile guide to museums developed in the late 90s. User requirements were collected via a survey to understand visitors’ profiles and visit styles in Natural Science museums. The knowledge acquired supported the specification of system requirements, helping defining user model, data structure and adaptive behaviour of the system. User requirements guided the design decisions on what could be implemented by using simple adaptable triggers and what instead needed more sophisticated adaptive techniques, a fundamental choice when all the computation must be done on a PDA. Graphical and interactive environments for developing and testing complex adaptive systems are discussed as a further step towards an iterative design that considers the user interaction a central point. The paper discusses how such an environment allows designers and developers to experiment with different system’s behaviours and to widely test it under realistic conditions by simulation of the actual context evolving over time. The understanding gained in HyperAudio is then considered in the perspective of the developments that followed that first experience: our findings seem still valid despite the passed time

The Challenges of Hardware Synthesis from C-like Languages

The relentless increase in the complexity of integrated circuits we can fabricate imposes a continuing need for ways to describe complex hardware succinctly. Because of their ubiquity and flexibility, many have proposed to use the C and C++ languages as specification languages for digital hardware. Yet, tools based on this idea have seen little commercial interest. In this paper, I argue that C/C++ is a poor choice for specifying hardware for synthesis and suggest a set of criteria that the next successful hardware description language should have

Automatic generation of hardware/software interfaces

Enabling new applications for mobile devices often requires the use of specialized hardware to reduce power consumption. Because of time-to-market pressure, current design methodologies for embedded applications require an early partitioning of the design, allowing the hardware and software to be developed simultaneously, each adhering to a rigid interface contract. This approach is problematic for two reasons: (1) a detailed hardware-software interface is difficult to specify until one is deep into the design process, and (2) it prevents the later migration of functionality across the interface motivated by efficiency concerns or the addition of features. We address this problem using the Bluespec Codesign Language~(BCL) which permits the designer to specify the hardware-software partition in the source code, allowing the compiler to synthesize efficient software and hardware along with transactors for communication between the partitions. The movement of functionality across the hardware-software boundary is accomplished by simply specifying a new partitioning, and since the compiler automatically generates the desired interface specifications, it eliminates yet another error-prone design task. In this paper we present BCL, an extension of a commercially available hardware design language (Bluespec SystemVerilog), a new software compiling scheme, and preliminary results generated using our compiler for various hardware-software decompositions of an Ogg Vorbis audio decoder, and a ray-tracing application.National Science Foundation (U.S.) (NSF (#CCF-0541164))National Research Foundation of Korea (grant from the Korean Government (MEST) (#R33-10095)

FPGA Based Accelerator for Hardware/Software Co-Simulation

在系统设计中,硬件复杂电路设计的调试与仿真工作对于设计者来说十分困难。为了降低仿真复杂度,加快仿真速度,本文提出利用fPgA加速的思想,实现软硬件协同加速仿真。经过实验,相对于纯软件仿真,利用软硬件协同加速仿真技术,仿真速度提高近30倍,大大缩短了仿真时间。In system deign,debugging for the design becomes increasingly difficult and designers want more efficient and high-performance verification and debugging solutions.As the design becomes larger and more complex,the pure software simulation suffers from the speed problem.In this paper,we present a new debugging methodology:FPGA based accelerator for hardware/software co-simulation.Experimental results show that the performance gain is up to 30 times over the pure software simulation

On the Recognition of Emotion from Physiological Data

This work encompasses several objectives, but is primarily concerned with an experiment where 33 participants were shown 32 slides in order to create ‗weakly induced emotions‘. Recordings of the participants‘ physiological state were taken as well as a self report of their emotional state. We then used an assortment of classifiers to predict emotional state from the recorded physiological signals, a process known as Physiological Pattern Recognition (PPR). We investigated techniques for recording, processing and extracting features from six different physiological signals: Electrocardiogram (ECG), Blood Volume Pulse (BVP), Galvanic Skin Response (GSR), Electromyography (EMG), for the corrugator muscle, skin temperature for the finger and respiratory rate. Improvements to the state of PPR emotion detection were made by allowing for 9 different weakly induced emotional states to be detected at nearly 65% accuracy. This is an improvement in the number of states readily detectable. The work presents many investigations into numerical feature extraction from physiological signals and has a chapter dedicated to collating and trialing facial electromyography techniques. There is also a hardware device we created to collect participant self reported emotional states which showed several improvements to experimental procedure

PML: UMA LINGUAGEM PARA MODELAGEM E AVALIAÇÃO DOS PROCESSADORES

Domain Specific Modelling Languages (DSMLs) inherit concepts of model-driven engineering aiming at defining components for software and hardware related to a specific domain. In this context, DSMLs usually are targeted to support more than one level of abstraction, bringing support to better understand the semantics of these components as well as enabling validation about their main concepts and relationships. Regarding hardware components modelling, specific languages may provide support on processing architectures models generation, easing architectural explorations for different configurations which in turn, can be tested against design constraints. In this context, this work presents a Domain Specific Modelling Languages called DSML (Processor Modelling Language) aiming at helping designers to efficiently design processing architectures . The language is supported by a tool  for editing and generation of models at different abstraction levels in SystemC. Thus, the generated models can be simulated, allowing functionality and conformity with design constraints exploration.Linguagens para Modelagem de Domínios Específicos fazem uso de preceitos da Engenharia Dirigida a Modelos para a definição de componentes de software e de hardware relacionados a um domínio específico. Nesse contexto, essas linguagens são concebidas para darem suporte a mais de um nível de abstração, além de trazer fácil conhecimento e validação a respeito da semântica e de possíveis relacionamentos entre estes. Em modelagem de componentes de hardware, podem oferecer suporte para geração de modelos simuláveis de arquiteturas de processadores, facilitando o projeto de diversas configurações a serem testadas frente às restrições de projeto. Nesse sentido, esse trabalho apresenta uma Linguagem de Domínio Específico chamada PML (Processor Modelling Language), para a especificação de modelos de arquiteturas de processadores, bem como uma ferramenta para edição e geração de descrições de processadores em diferentes níveis de abstração. Essas descrições são simuláveis podendo então serem avaliadas em relação às suas funcionalidades, restrições de projeto e desempenho de simulação