Underwater acoustic communications and adaptive signal processing

This dissertation proposes three new algorithms for underwater acoustic wireless communications. One is a new tail-biting circular MAP decoder for full tail-biting convolution (FTBC) codes for very short data blocks intended for Internet of Underwater Things (IoUT). The proposed algorithm was evaluated by ocean experiments and computer simulations on both Physical (PHY) and Media access control (MAC) layers. The ocean experimental results show that without channel equalization, the full tail-biting convolution (FTBC) codes with short packet lengths not only can perform similarly to zero-tailing convolution (ZTC) codes in terms of bit error rate (BER) in the PHY layer. Computer simulation results show that the FTBC codes outperform the ZTC codes in terms of MAC layer metrics, such as collision rate and bandwidth utilization, in a massive network of battery powered IoUT devices. Second, this dissertation also proposes a new approach to utilizing the underwater acoustic (UWA) wireless communication signals acquired in a real-world experiment as a tool for evaluating new coding and modulation schemes in realistic doubly spread UWA channels. This new approach, called passband data reuse, provides detailed procedures for testing the signals under test (SUT) that change or add error correction coding, change bit to symbol mapping (baseband modulation) schemes from a set of original experimental data --Abstract, page iv

Deep Ensemble of Weighted Viterbi Decoders for Tail-Biting Convolutional Codes

Tail-biting convolutional codes extend the classical zero-termination convolutional codes: Both encoding schemes force the equality of start and end states, but under the tail-biting each state is a valid termination. This paper proposes a machine-learning approach to improve the state-of-the-art decoding of tail-biting codes, focusing on the widely employed short length regime as in the LTE standard. This standard also includes a CRC code. First, we parameterize the circular Viterbi algorithm, a baseline decoder that exploits the circular nature of the underlying trellis. An ensemble combines multiple such weighted decoders, each decoder specializes in decoding words from a specific region of the channel words' distribution. A region corresponds to a subset of termination states; the ensemble covers the entire states space. A non-learnable gating satisfies two goals: it filters easily decoded words and mitigates the overhead of executing multiple weighted decoders. The CRC criterion is employed to choose only a subset of experts for decoding purpose. Our method achieves FER improvement of up to 0.75dB over the CVA in the waterfall region for multiple code lengths, adding negligible computational complexity compared to the circular Viterbi algorithm in high SNRs

Reversed-Trellis Tail-Biting Convolutional Code (RT-TBCC) Decoder Architecture Design for LTE

Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixed-tail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximum-likelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed