2,246 research outputs found
Stirling Convertor Control for a Lunar Concept Rover
NASA Glenn Research Center is developing various circuits for a lunar concept rover powered by both a stirling convertor and lithium ion batteries. To begin, a survey of six analog, non-power factor correcting controllers was done for an Advanced Stirling Convertor (ASC) design one was selected to control the stirling convertor. Next, a constant power circuit and lithium ion battery charger was designed, built and tested based on simulation in PSpice. The constant power circuit enables the stirling convertor to maintain a constant power when additional power is required from the batterie
An agile supply modulator with improved transient performance for power efficient linear amplifier employing envelope tracking techniques
This article presents an agile supply modulator with optimal transient performance that includes improvement in rise time, overshoot and settling time for the envelope tracking supply in linear power amplifiers. For this purpose, we propose an on-demand current source module: the bang-bang transient performance enhancer (BBTPE). Its objective is to follow fast variations in input signals with reduced overshoot and settling time without deteriorating the steady-state performance of the buck regulator. The proposed approach enables fast system response through the BBTPE and an accurate steady-state output response through a low switching ripple and power efficient dynamic buck regulator. Fast output response with the help of the added module induces a slower rise of inductor current in the buck converter that further helps the proposed system to reduce both overshoot and settling time. This article also introduces an efficient selective tracking of envelope signal for linear PAs. To demonstrate the feasibility of the proposed solution, extensive simulations and experimental results from a discrete system are reported. The proposed supply modulator shows 80% improvement in rise time along with 60% reduction in both overshoot and settling time compared to the conventional dynamic buck regulator-based solution. Experimental results using the LTE 16-QAM 5 MHz standard shows improvement of 7.68 dB and 65.1% in adjacent channel power ratio (ACPR) and error vector magnitude (EVM), respectively.Peer ReviewedPostprint (author's final draft
Modeling and analysis of power processing systems: Feasibility investigation and formulation of a methodology
A review is given of future power processing systems planned for the next 20 years, and the state-of-the-art of power processing design modeling and analysis techniques used to optimize power processing systems. A methodology of modeling and analysis of power processing equipment and systems has been formulated to fulfill future tradeoff studies and optimization requirements. Computer techniques were applied to simulate power processor performance and to optimize the design of power processing equipment. A program plan to systematically develop and apply the tools for power processing systems modeling and analysis is presented so that meaningful results can be obtained each year to aid the power processing system engineer and power processing equipment circuit designers in their conceptual and detail design and analysis tasks
Doctor of Philosophy
dissertationHigh speed wireless communication systems (e.g., long-term evolution (LTE), Wi-Fi) operate with high bandwidth and large peak-to-average power ratios (PAPRs). This is largely due to the use of orthogonal frequency division multiplexing (OFDM) modulation that is prevalent to maximize the spectral efficiency of the communication system. The power amplifier (PA) in the transmitter is the dominant energy consumer in the radio, largely because of the PAPR of the input signal. To reduce the energy consumption of the PA an amplifier that simultaneously achieves high efficiency and high linearity. Furthermore, to lower the cost for high volume production, it is desirable to achieve a complete System-on-Chip (SoC) integration. Linear amplifiers (e.g., Class-A, -B, -AB) are inefficient when amplifying signals with large PAPR that is associated by high peak-to-average modulation techniques such as LTE. OFDM. Switching amplifiers (e.g., Class-D, -E, -F) are very promising due to their high efficiency when compared to their linear amplifier counterparts. Linearization techniques for switching amplifiers have been intensively investigated due to their limited sensitivity to the input amplitude of the signal. Deep-submicron CMOS technology is mostly utilized for logic circuitry, and the Moore's law scaling of CMOS optimizes transistors to operate as high-speed and low-loss switches rather than high gain transistors. Hence, it is advantageous to use transistors in switching mode as switching amplifies and use high-speed digital logic circuitry to implement linearization systems and circuitry. In this work, several linearization architectures are investigated and demonstrated. An envelope elimination and restoration (EER) transmitter that comprises a class-E power amplifier and a 10-bit digital-to-analog converter (DAC) controlled current modulator is investigated. A pipelined switched-capacitor DAC is designed to control an open-loop transconductor that operates as a current modulator, modulating the amplitude of the current supplied to a class-E PA. Such a topology allows for increased filtering of the quantization noise that is problematic in most digital PAs (DPA). The proposed quadrature and multiphase architecture can avoid the bandwidth expansion and delay mismatch associated with polar PAs. The multiphase switched capacitor power amplifier (SCPA) was proposed after the quadrature SCPA and it significantly improves the power efficiency
Control strategy for a modified cascade multilevel inverter with dual DC source for enhanced drivetrain operation
This paper presents a new control strategy for a modified cascade multilevel inverter used in drivetrain operations. The proposed inverter is a three-phase bridge with its dc link fed by a dc source (battery), and each phase series-connected respectively to an H-bridge fed with a floating dc source (ultracapacitor). To exploit the potentials of the inverter for enhanced drivetrain performance, a sophisticated yet efficient modulation method is proposed to optimise energy transfer between the dc sources and with the load (induction motor) during typical operations, and to minimise switching losses and harmonics distortion. Detailed analysis of the proposed control method is presented, which is supported by experimental verifications
A survey on RF and microwave doherty power amplifier for mobile handset applications
This survey addresses the cutting-edge load modulation microwave and radio frequency power amplifiers for next-generation wireless communication standards. The basic operational principle of the Doherty amplifier and its defective behavior that has been originated by transistor characteristics will be presented. Moreover, advance design architectures for enhancing the Doherty power amplifier’s performance in terms of higher efficiency and wider bandwidth characteristics, as well as the compact design techniques of Doherty amplifier that meets the requirements of legacy 5G handset applications, will be discussed.Agencia Estatal de Investigación | Ref. TEC2017-88242-C3-2-RFundação para a Ciência e a Tecnologia | Ref. UIDP/50008/201
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuit’s key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuit’s
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais rápidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicações que
requerem sensores de imagem, o prĂłximo salto tecnolĂłgico no ramo dos sensores de imagem Ă©
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia “3D-stacked”. O empilhamento de chips é relativamente recente e é uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vários planos de silĂcio com diferentes
funções poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de pĂxeis. AlĂ©m disso, num sensor de
imagem de planos de silĂcio empilhados, os circuitos de leitura estĂŁo posicionados debaixo da
matriz de pĂxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruĂdo e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho Ă© o de desenhar circuitos de leitura de coluna de muito baixo ruĂdo,
planeados para serem empregues em sensores de imagem “3D-stacked” com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura sĂŁo de baixo ruĂdo,
rapidez e pouca área utilizada, de forma a obter-se o melhor rácio.
Uma breve revisĂŁo histĂłrica dos sensores de imagem CMOS Ă© apresentada, seguida da
motivação, dos objetivos e das contribuições feitas. Os fundamentos dos sensores de imagem
CMOS sĂŁo tambĂ©m abordados para expor as suas caracterĂsticas, os blocos essenciais, os tipos
de operação, assim como as suas caracterĂsticas fĂsicas e suas mĂ©tricas de avaliação. No
seguimento disto, especial atenção Ă© dada Ă teoria subjacente ao ruĂdo inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possĂveis aspetos que dificultem
atingir a tĂŁo desejada performance de muito baixo ruĂdo. Por fim, os resultados experimentais
do sensor desenvolvido sĂŁo apresentados junto com possĂveis conjeturas e respetivas conclusões,
terminando o documento com o assunto de empilhamento vertical de camadas de silĂcio, junto
com o possĂvel trabalho futuro
CMOS Data Converters for Closed-Loop mmWave Transmitters
With the increased amount of data consumed in mobile communication systems, new solutions for the infrastructure are needed. Massive multiple input multiple output (MIMO) is seen as a key enabler for providing this increased capacity. With the use of a large number of transmitters, the cost of each transmitter must be low. Closed-loop transmitters, featuring high-speed data converters is a promising option for achieving this reduced unit cost.In this thesis, both digital-to-analog (D/A) and analog-to-digital (A/D) converters suitable for wideband operation in millimeter wave (mmWave) massive MIMO transmitters are demonstrated. A 2
76 bit radio frequency digital-to-analog converter (RF-DAC)-based in-phase quadrature (IQ) modulator is demonstrated as a compact building block, that to a large extent realizes the transmit path in a closed-loop mmWave transmitter. The evaluation of an successive-approximation register (SAR) analog-to-digital converter (ADC) is also presented in this thesis. Methods for connecting simulated and measured performance has been studied in order to achieve a better understanding about the alternating comparator topology.These contributions show great potential for enabling closed-loop mmWave transmitters for massive MIMO transmitter realizations
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