405 research outputs found

    Improving practical sensitivity of energy optimized wake-up receivers: proof of concept in 65nm CMOS

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    We present a high performance low-power digital base-band architecture, specially designed for an energy optimized duty-cycled wake-up receiver scheme. Based on a careful wake-up beacon design, a structured wake-up beacon detection technique leads to an architecture that compensates for the implementation loss of a low-power wake-up receiver front-end at low energy and area costs. Design parameters are selected by energy optimization and the architecture is easily scalable to support various network sizes. Fabricated in 65nm CMOS, the digital base-band consumes 0.9uW (V_DD=0.37V) in sub-threshold operation at 250kbps, with appropriate 97% wake-up beacon detection and 0.04% false alarm probabilities. The circuit is fully functional at a minimum V_DD of 0.23V at f_max=5kHz and 0.018uW power consumption. Based on these results we show that our digital base-band can be used as a companion to compensate for front-end implementation losses resulting from the limited wake-up receiver power budget at a negligible cost. This implies an improvement of the practical sensitivity of the wake-up receiver, compared to what is traditionally reported.Comment: Submitted to IEEE Sensors Journa

    To Develop and Implement Low Power, High Speed VLSI for Processing Signals using Multirate Techniques

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    Multirate technique is necessary for systems with different input and output sampling rates. Recent advances in mobile computing and communication applications demand low power and high speed VLSI DSP systems [4]. This Paper presents Multirate modules used for filtering to provide signal processing in wireless communication system. Many architecture developed for the design of low complexity, bit parallel Multiple Constant Multiplications operation which dominates the complexity of DSP systems. However, major drawbacks of present approaches are either too costly or not efficient enough. On the other hand, MCM and digit-serial adder offer alternative low complexity designs, since digit-serial architecture occupy less area and are independent of the data word length [1][10]. Multiple Constant Multiplications is efficient way to reduce the number of addition and subtraction in polyphase filter implementation. This Multirate design methodology is systematic and applicable to many problems. In this paper, attention has given to the MCM & digit serial architecture with shifting and adding techniques that offers alternative low complexity in operations. This paper also focused on Multirate Signal Processing Modules using Voltage and Technology scaling. Reduction of power consumption is important for VLSI system and also it becomes one of the most critical design parameter. Transistorized Multirate module which has full custom design with different circuit topology and optimization level simulated on cadence platform. Multirate modules are used AMI 0.6 um, TSMC 0.35 um, and TSMC 0.25 um technologies for different voltage scaling. The presented methodology provides a systematic way to derive circuit technique for high speed operation at a low supply voltage. Multirate polyphase interpolator and decimator are also designed and optimized at architectural level in order to analyze the terms power consumption, area and speed. DOI: 10.17762/ijritcc2321-8169.150314

    Design of Multistage Decimation Filters Using Cyclotomic Polynomials: Optimization and Design Issues

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    This paper focuses on the design of multiplier-less decimation filters suitable for oversampled digital signals. The aim is twofold. On one hand, it proposes an optimization framework for the design of constituent decimation filters in a general multistage decimation architecture. The basic building blocks embedded in the proposed filters belong, for a simple reason, to the class of cyclotomic polynomials (CPs): the first 104 CPs have a z-transfer function whose coefficients are simply {-1,0,+1}. On the other hand, the paper provides a bunch of useful techniques, most of which stemming from some key properties of CPs, for designing the proposed filters in a variety of architectures. Both recursive and non-recursive architectures are discussed by focusing on a specific decimation filter obtained as a result of the optimization algorithm. Design guidelines are provided with the aim to simplify the design of the constituent decimation filters in the multistage chain.Comment: Submitted to CAS-I, July 07; 11 pages, 5 figures, 3 table

    A programmable CMOS decimator for sigma-delta analog-to-digital converter and charge pump circuits

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    PROGRAMMABLE DECIMATOR FOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTER: In this work a programmable decimator design has been presented in 1.5 μm n-well CMOS process for integration with an existing modulator to form a sigma-delta analog-to-digital converter (ADC). The decimator is implemented using a second order Cascaded Integrator Comb (CIC) filter and can be programmed to work with two different oversampling ratios of 64 and 16. The input to the decimator is provided from a first order modulator. With oversampling ratios of 64 and 16, an output resolution of 10-bit and 7-bit, respectively are achieved for the ADC. The ADC can be operated with an oversampling clock frequency of up to 8 MHz and with an input signal bandwidth of up to 65 KHz. An in-built clock divider circuit has been designed which generates two output clocks whose frequencies are equal to the input clock frequency divided by the oversampling ratios 64 and 16. CHARGE PUMP CIRCUITS: The charge pump CMOS circuits are presented which are designed based on a new technique of internal clock voltage boosting. Four and six-stage charge pumps are implemented in 1.5 μm n-well CMOS process. The charge pump circuits can be operated in 1.2 V - 3 V power supply voltage range. Outputs of 12.5 V and 17.8 V are measured from four and six-stage charge pumps, respectively with a 3 V power supply. The charge pump circuits can also be used to generate clock voltages higher than the input clock voltage. In the present design, clock voltages of 8 V and 11 V have been generated from four-stage and six-stage charge pumps, respectively which are nearly 2.5 and 4 times the input clock voltage of 3 V. The technique of boosting the clock internally has been applied in implementation of a revised version of battery powered Bio-implantable Electrical Stimulation System (BESS) integrated circuit

    Low power, reduced complexity filtering and improved tracking accuracy for GNSS

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    This thesis addresses the power consumption problems resulting from the advent of multiple GNSS satellite systems which create the need for receivers supporting multi-frequency, multi-constellation GNSS systems. Such a multi-mode receiver requires a substantial amount of signal processing power which translates to increased hardware complexity and higher power dissipation which reduces the battery life of a mobile platform. During the course of the work undertaken, a power analysis tool was developed in order to be able to estimate the hardware utilisation as well as the power consumption of a digital system. By using the power estimation tool developed, it was established that most of the power was dissipated after the Analog to Digital Converter (ADC)by the filters associated with the decimation process. The power dissipation and the hardware complexity of the decimator can be reduced substantially by using a minimum-phase Infinite Impulse Response (IIR) filter. For Global Positioning System (GPS) civilian signals, the use of IIR filters does not deleteriously affect the positional accuracy. However, in the case where an IIR filter was deployed in a GLObalnaya NAvigatsionnaya Sputnikovaya Sistema (GLONASS) receiver, the pseudorange measurements of the receiver varied by up to 200 metres. The work undertaken proposes various methods that overcomes the pseudorange measurement variation and reports on the results that are on par with linear-phase Finite Impulse Response (FIR) filters. The work also proposes a modified tracking loop that is capable of tracking very low Doppler frequencies without decreasing the tracking performance

    Third order CMOS decimator design for sigma delta modulators

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    A third order Cascaded Integrated Comb (CIC) filter has been designed in 0.5μm n-well CMOS process to interface with a second order oversampling sigma-delta ADC modulator. The modulator was designed earlier in 0.5μm technology. The CIC filter is designed to operate with 0 to 5V supply voltages. The modulator is operated with ±2.5V supply voltage and a fixed oversampling ratio of 64. The CIC filter designed includes integrator, differentiator blocks and a dedicated clock divider circuit, which divides the input clock by 64. The CIC filter is designed to work with an ADC that operates at a maximum oversampling clock frequency of up to 25 MHz and with baseband signal bandwidth of up to 800 kHz. The design and performance of the CIC filter fabricated has been discussed
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