Advanced Message Routing for Scalable Distributed Simulations

The Joint Forces Command (JFCOM) Experimentation Directorate (J9)'s recent Joint Urban Operations (JUO) experiments have demonstrated the viability of Forces Modeling and Simulation in a distributed environment. The JSAF application suite, combined with the RTI-s communications system, provides the ability to run distributed simulations with sites located across the United States, from Norfolk, Virginia to Maui, Hawaii. Interest-aware routers are essential for communications in the large, distributed environments, and the current RTI-s framework provides such routers connected in a straightforward tree topology. This approach is successful for small to medium sized simulations, but faces a number of significant limitations for very large simulations over high-latency, wide area networks. In particular, traffic is forced through a single site, drastically increasing distances messages must travel to sites not near the top of the tree. Aggregate bandwidth is limited to the bandwidth of the site hosting the top router, and failures in the upper levels of the router tree can result in widespread communications losses throughout the system. To resolve these issues, this work extends the RTI-s software router infrastructure to accommodate more sophisticated, general router topologies, including both the existing tree framework and a new generalization of the fully connected mesh topologies used in the SF Express ModSAF simulations of 100K fully interacting vehicles. The new software router objects incorporate the scalable features of the SF Express design, while optionally using low-level RTI-s objects to perform actual site-to-site communications. The (substantial) limitations of the original mesh router formalism have been eliminated, allowing fully dynamic operations. The mesh topology capabilities allow aggregate bandwidth and site-to-site latencies to match actual network performance. The heavy resource load at the root node can now be distributed across routers at the participating sites

Virtual Prototyping for Dynamically Reconfigurable Architectures using Dynamic Generic Mapping

This paper presents a virtual prototyping methodology for Dynamically Reconfigurable (DR) FPGAs. The methodology is based around a library of VHDL image processing components and allows the rapid prototyping and algorithmic development of low-level image processing systems. For the effective modelling of dynamically reconfigurable designs a new technique named, Dynamic Generic Mapping is introduced. This method allows efficient representation of dynamic reconfiguration without needing any additional components to model the reconfiguration process. This gives the designer more flexibility in modelling dynamic configurations than other methodologies. Models created using this technique can then be simulated and targeted to a specific technology using the same code. This technique is demonstrated through the realisation of modules for a motion tracking system targeted to a DR environment, RIFLE-62

iTETRIS Platform Architecture for the Integration of Cooperative Traffic and Wireless Simulations

The use of cooperative wireless communications can support driving through dynamic exchange of Vehicle-to-Vehicle (V2V) and Vehicle-to-Infrastructure (V2I) messages. Traffic applications based on such systems will be able to generate a safer, faster, cheaper and cleaner way for people and goods to move. In this context, the iTERIS project aims at providing the framework to combine traffic mobility and wireless communication simulations for large scale testing of traffic management solutions based on cooperative systems. This paper addresses the description and explanation of the implementation choices taken to build a modular and interoperable architecture integrating heterogeneous traffic and wireless simulators, and application algorithms supporting traffic management strategies. The functions of an “in-between” control system for managing correct simulation executions over the platform are presented. The inter-block interaction procedures identified to ensure optimum data transfer for simulation efficiency are also introduced

Simulation and Visualization of Thermal Metaphor in a Virtual Environment for Thermal Building Assessment

La référence est présente sur HAL mais est incomplète (il manque les co-auteurs et le fichier pdf).The current application of the design process through energy efficiency in virtual reality (VR) systems is limited mostly to building performance predictions, as the issue of the data formats and the workflow used for 3D modeling, thermal calculation and VR visualization. The importance of energy efficiency and integration of advances in building design and VR technology have lead this research to focus on thermal simulation results visualized in a virtual environment to optimize building design, particularly concerning heritage buildings. The emphasis is on the representation of thermal data of a room simulated in a virtual environment (VE) in order to improve the ways in which thermal analysis data are presented to the building stakeholder, with the aim of increasing accuracy and efficiency. The approach is to present more immersive thermal simulation and to project the calculation results in projective displays particularly in Immersion room (CAVE-like). The main idea concerning the experiment is to provide an instrument of visualization and interaction concerning the thermal conditions in a virtual building. Thus the user can immerge, interact, and perceive the impact of the modifications generated by the system, regarding the thermal simulation results. The research has demonstrated it is possible to improve the representation and interpretation of building performance data, particularly for thermal results using visualization techniques.Direktorat Riset dan Pengabdian Masyarakat (DRPM) Universitas Indonesia Research Grant No. 2191/H2.R12/HKP.05.00/201

Enabling Disaster Resilient 4G Mobile Communication Networks

The 4G Long Term Evolution (LTE) is the cellular technology expected to outperform the previous generations and to some extent revolutionize the experience of the users by taking advantage of the most advanced radio access techniques (i.e. OFDMA, SC-FDMA, MIMO). However, the strong dependencies between user equipments (UEs), base stations (eNBs) and the Evolved Packet Core (EPC) limit the flexibility, manageability and resiliency in such networks. In case the communication links between UEs-eNB or eNB-EPC are disrupted, UEs are in fact unable to communicate. In this article, we reshape the 4G mobile network to move towards more virtual and distributed architectures for improving disaster resilience, drastically reducing the dependency between UEs, eNBs and EPC. The contribution of this work is twofold. We firstly present the Flexible Management Entity (FME), a distributed entity which leverages on virtualized EPC functionalities in 4G cellular systems. Second, we introduce a simple and novel device-todevice (D2D) communication scheme allowing the UEs in physical proximity to communicate directly without resorting to the coordination with an eNB.Comment: Submitted to IEEE Communications Magazin

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared.Comment: 15 pages, 10 figures (11 figure files), submitted to Journal of Instrumentatio