Self-Reconfigurable Analog Arrays: Off-The Shelf Adaptive Electronics for Space Applications

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from benefits of rapid prototyping. This forces them to expensive and lengthy custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitations come from two directions: commercial Field Programmable Analog Arrays (FPAA) have limited variability in the components offered on-chip; and they are only qualified for best case scenarios for military grade (-55C to +125C). In order to avoid huge overheads, there is a growing trend towards avoiding thermal and radiation protection by developing extreme environment electronics, which maintain correct operation while exposed to temperature extremes (-180degC to +125degC). This paper describes a recent FPAA design, the Self-Reconfigurable Analog Array (SRAA) developed at JPL. It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures

Stellar intensity interferometry: Experimental steps toward long-baseline observations

Experiments are in progress to prepare for intensity interferometry with arrays of air Cherenkov telescopes. At the Bonneville Seabase site, near Salt Lake City, a testbed observatory has been set up with two 3-m air Cherenkov telescopes on a 23-m baseline. Cameras are being constructed, with control electronics for either off- or online analysis of the data. At the Lund Observatory (Sweden), in Technion (Israel) and at the University of Utah (USA), laboratory intensity interferometers simulating stellar observations have been set up and experiments are in progress, using various analog and digital correlators, reaching 1.4 ns time resolution, to analyze signals from pairs of laboratory telescopes.Comment: 12 pages, 3 figur

An On-line BIST RAM Architecture with Self Repair Capabilities

The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed. In this context, RAM (random access memories) are among the most critical components. This paper proposes a built-in self-repair (BISR) approach for RAM cores. The proposed design, introducing minimal and technology-dependent overheads, can detect and repair a wide range of memory faults including: stuck-at, coupling, and address faults. The test and repair capabilities are used on-line, and are completely transparent to the external user, who can use the memory without any change in the memory-access protocol. Using a fault-injection environment that can emulate the occurrence of faults inside the module, the effectiveness of the proposed architecture in terms of both fault detection and repairing capability was verified. Memories of various sizes have been considered to evaluate the area-overhead introduced by this proposed architectur

A Methodology to Perform Online Self-Testing for Field-Programmable Analog Array Circuits

This paper presents a methodology to perform online self-testing for analog circuits implemented on field-programmable analog arrays (FPAAs). It proposes to partition the FPAA circuit under test into subcircuits. Each subcircuit is tested by replicating the subcircuit with programmable resources on the FPAA chip, and comparing the outputs of the subcircuit and its replication. To effectively implement the proposed methodology, this paper proposes a simple circuit partition method and develops techniques to address circuit stability problems that are often encountered in the proposed testing method. Furthermore, error sources in the proposed testing circuit are studied and methods to improve the accuracy of testing results are presented. Finally, experimental results are presented to demonstrate the validity of the proposed methodology

Built-In-Self-Testing Techniques for Programmable Capacitor Arrays

Programmable capacitor arrays (PCA) are frequently used in reconfigurable analog circuits. Since PCA can be programmed to numerous values, testing PCA by exhaustively examining all PCA values can lead to lengthy testing processes. To address this problem, we present an efficient built-in-self-testing (BIST) method for PCA used in reconfigurable analog circuits. The proposed BIST method takes advantage of existing programmable resources and, hence, introduces very small hardware overhead. Additionally, we present two simple and effective capacitor comparison techniques for implementing the proposed BIST method. The accuracy of the proposed circuit techniques is investigated and closed-form equations are derived for estimating comparison accuracy that can be achieved by the proposed techniques. Finally, circuit simulations are performed to validate the proposed techniques

Non-classical computing: feasible versus infeasible

Physics sets certain limits on what is and is not computable. These limits are very far from having been reached by current technologies. Whilst proposals for hypercomputation are almost certainly infeasible, there are a number of non classical approaches that do hold considerable promise. There are a range of possible architectures that could be implemented on silicon that are distinctly different from the von Neumann model. Beyond this, quantum simulators, which are the quantum equivalent of analogue computers, may be constructable in the near future