221,366 research outputs found
Digital IP Protection Using Threshold Voltage Control
This paper proposes a method to completely hide the functionality of a
digital standard cell. This is accomplished by a differential threshold logic
gate (TLG). A TLG with inputs implements a subset of Boolean functions of
variables that are linear threshold functions. The output of such a gate is
one if and only if an integer weighted linear arithmetic sum of the inputs
equals or exceeds a given integer threshold. We present a novel architecture of
a TLG that not only allows a single TLG to implement a large number of complex
logic functions, which would require multiple levels of logic when implemented
using conventional logic primitives, but also allows the selection of that
subset of functions by assignment of the transistor threshold voltages to the
input transistors. To obfuscate the functionality of the TLG, weights of some
inputs are set to zero by setting their device threshold to be a high .
The threshold voltage of the remaining transistors is set to low to
increase their transconductance. The function of a TLG is not determined by the
cell itself but rather the signals that are connected to its inputs. This makes
it possible to hide the support set of the function by essentially removing
some variable from the support set of the function by selective assignment of
high and low to the input transistors. We describe how a standard cell
library of TLGs can be mixed with conventional standard cells to realize
complex logic circuits, whose function can never be discovered by reverse
engineering. A 32-bit Wallace tree multiplier and a 28-bit 4-tap filter were
synthesized on an ST 65nm process, placed and routed, then simulated including
extracted parastics with and without obfuscation. Both obfuscated designs had
much lower area (25%) and much lower dynamic power (30%) than their
nonobfuscated CMOS counterparts, operating at the same frequency
Pigmentation pattern formation in butterflies: experiments and models
Butterfly pigmentation patterns are one of the most spectacular and vivid examples of pattern formation in biology. They have attracted much attention from experimentalists and theoreticians, who have tried to understand the underlying genetic, chemical and physical processes that lead to patterning. In this paper, we present a brief review of this field by first considering the generation of the localised, eyespot, patterns and then the formation of more globally controlled patterns. We present some new results applied to pattern formation on the wing of the mimetic butterfly Papilio dardanus. To cite this article: H.F. Nijhout et al., C. R. Biologies 326 (2003)
Nonlinear Design Technique for High-Power Switching-Mode Oscillators
A simple nonlinear technique for the design of high-efficiency and high-power switching-mode oscillators is presented. It combines existing quasi-nonlinear methods and the use of an auxiliary generator (AG) in harmonic balance. The AG enables the oscillator optimization to achieve high output power and dc-to-RF conversion efficiency without affecting the oscillation frequency. It also imposes a sufficient drive on the transistor to enable the switching-mode operation with high efficiency. Using this AG, constant-power and constant-efficiency contour plots are traced in order to determine the optimum element values. The oscillation startup condition and the steady-state stability are analyzed with the pole-zero identification technique. The influence of the gate bias on the output power, efficiency, and stability is also investigated. A class-E oscillator is demonstrated using the proposed technique. The oscillator exhibits 75 W with 67% efficiency at 410 MHz
Synthesis of neural networks for spatio-temporal spike pattern recognition and processing
The advent of large scale neural computational platforms has highlighted the
lack of algorithms for synthesis of neural structures to perform predefined
cognitive tasks. The Neural Engineering Framework offers one such synthesis,
but it is most effective for a spike rate representation of neural information,
and it requires a large number of neurons to implement simple functions. We
describe a neural network synthesis method that generates synaptic connectivity
for neurons which process time-encoded neural signals, and which makes very
sparse use of neurons. The method allows the user to specify, arbitrarily,
neuronal characteristics such as axonal and dendritic delays, and synaptic
transfer functions, and then solves for the optimal input-output relationship
using computed dendritic weights. The method may be used for batch or online
learning and has an extremely fast optimization process. We demonstrate its use
in generating a network to recognize speech which is sparsely encoded as spike
times.Comment: In submission to Frontiers in Neuromorphic Engineerin
Nonlinear Switched-Capacitor Networks: Basic Principles and Piecewise-Linear Design
The applicability of switched-capacitor (SC) components to the design of nonlinear networks is extensively discussed in this paper. The main objective is to show that SC's can be efficiently used for designing nonlinear networks. Moreover, the design methods to be proposed here are fully compatible with general synthesis methods for nonlinear n -ports. Different circuit alternatives are given and their potentials are evaluated.Office of Naval Research (USA) N00014-76-C-0572Comisión Interministerial de Ciencia y Tecnología 0235/81Semiconductor Research Corporation (USA) 82-11-00
A practical floating-gate Muller-C element using vMOS threshold gates
This paper presents the rationale for vMOS-based realizations of digital circuits when logic design techniques based on threshold logic gates are used. Some practical problems in the vMOS implementation of threshold gates have been identified and solved. The feasibility and versatility of the proposed technique as well as its potential as a low-cost design technique for CMOS technologies have been shown by experimental results from a multiple-input Muller C-element. The proposed new realization exhibits better performance related to delay and area and power consumption than the traditional logic implementation
Conformal phased array with beam forming for airborne satellite communication
For enhanced communication on board of aircraft novel antenna systems with broadband satellite-based capabilities are required. The installation of such systems on board of aircraft requires the development of a very low-profile aircraft antenna, which can point to satellites anywhere in the upper hemisphere. To this end, phased array antennas which are conformal to the aircraft fuselage are attractive. In this paper two key aspects of conformal phased array antenna arrays are addressed: the development of a broadband Ku-band antenna and the beam synthesis for conformal array antennas. The antenna elements of the conformal array are stacked patch antennas with dual linear polarization which have sufficient bandwidth. For beam forming synthesis a method based on a truncated Singular Value Decomposition is proposed
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