50 research outputs found

    Track-Initiated Beam Spoiling for Improved Tracking with Digital Phased-Array Radars

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    Radar systems have become highly dynamic with the advancements in all-digital radar architectures. All-digital radar architectures introduce the potential for dynamic beamforming. This thesis will detail the fundamentals that are the foundation of radar signal processing (RSP) and modeling a digital phased array radar. This thesis will detail the techniques used for digital beamspoiling. The intentional beamspoiling is intended to improve the trackers’ ability to track a target continuously. When a high-speed target falls out of a beam due to a maneuver, the radar will spoil the transmit beam illuminating a wider scene. The wider illuminated scene allows for a higher likelihood of accurately detecting the target, allowing the tracker to track the target continuously. This thesis will discuss the theory and application of the trackers used in the simulation. With the beamspoiling and trackers, this thesis will analyze the ability of an all-digital phased array to track a target utilizing dynamic beamforming to improve the tracking performance. Finally, it will detail the improvement of the trackers’ ability to track when utilizing beamspoiling for specific situations, allowing the radar to track targets for a more extended time. The results varied based on the amount a transmit beam was spoiled due to the loss in SNR that naturally occurs from the decrease in power density

    Analysis and optimization of a debug post-silicon hardware architecture

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    The goal of this thesis is to analyze the post-silicon validation hardware infrastructure implemented on multicore systems taking as an example Esperanto Technologies SoC, which has thousands of RISC-V processors and targets specific software applications. Then, based on the conclusions of the analysis, the project proposes a new post-silicon debug architecture that can fit on any System on-Chip without depending on its target application or complexity and that optimizes the options available on the market for multicore systems

    Advanced Applications of Rapid Prototyping Technology in Modern Engineering

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    Rapid prototyping (RP) technology has been widely known and appreciated due to its flexible and customized manufacturing capabilities. The widely studied RP techniques include stereolithography apparatus (SLA), selective laser sintering (SLS), three-dimensional printing (3DP), fused deposition modeling (FDM), 3D plotting, solid ground curing (SGC), multiphase jet solidification (MJS), laminated object manufacturing (LOM). Different techniques are associated with different materials and/or processing principles and thus are devoted to specific applications. RP technology has no longer been only for prototype building rather has been extended for real industrial manufacturing solutions. Today, the RP technology has contributed to almost all engineering areas that include mechanical, materials, industrial, aerospace, electrical and most recently biomedical engineering. This book aims to present the advanced development of RP technologies in various engineering areas as the solutions to the real world engineering problems

    SpiNNaker - A Spiking Neural Network Architecture

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    20 years in conception and 15 in construction, the SpiNNaker project has delivered the world’s largest neuromorphic computing platform incorporating over a million ARM mobile phone processors and capable of modelling spiking neural networks of the scale of a mouse brain in biological real time. This machine, hosted at the University of Manchester in the UK, is freely available under the auspices of the EU Flagship Human Brain Project. This book tells the story of the origins of the machine, its development and its deployment, and the immense software development effort that has gone into making it openly available and accessible to researchers and students the world over. It also presents exemplar applications from ‘Talk’, a SpiNNaker-controlled robotic exhibit at the Manchester Art Gallery as part of ‘The Imitation Game’, a set of works commissioned in 2016 in honour of Alan Turing, through to a way to solve hard computing problems using stochastic neural networks. The book concludes with a look to the future, and the SpiNNaker-2 machine which is yet to come

    Feasibility study and emulation of the Hough Transform algorithm on FPGA devices for ATLAS Phase-II trigger upgrade

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    In the next 10 years, a radical upgrade is expected for the Large Hadron Collider focused in achieving the highest values in the instantaneous and integrated luminosity. Both the subdetectrors of the experiments and their data acquisition systems will need an upgrade. For the Phase-II upgrade of the Trigger and Data Acquisition System (TDAQ) of the ATLAS experiment a common platform has been created to share the common firmware, software and tools that are ongoing and that will come in the next years within the ATLAS TDAQ collaboration. The environment includes a set of design procedures, a virtual machine as repository for the firmware and some automatic tools for the continuous integration and versioning. The platform is under testing, as the firmware will be tested on the TDAQ upgraded, it will also be used for the prototype cards that will be produced as demonstrator for the ATLAS Hardware Tracking for the Trigger (HTT) system. For the HTT project a physical environment is being prepared, exploiting Peripheral Component Interconnect express (PCIe) and ACTA crates. My personal work has been the design of a part of track-fitting algorithms, in particular the one using the Hough Transform. This implementation has been required by the ATLAS experiment as an alternative solution to the baseline proposal accepted and described in the TDAQ Upgrade Technical Design Report (TDR). I have developed and tested a set of pattern vectors used not only in the simulation and validation of the algorithm, but also in the hadware integration on a FPGA based hardware accelerator. The used technology is based on high-performance Xilinx Ultrascale+ FPGA, implemented on VCU1525 board. This work is going to be validated by the ATLAS collaboration very soon, so to understand how we can proceed in the future upgrade. Bologna is the only Italian institute which participates in the integration of a tracking algorithm in the ATLAS trigger upgrade, using high performance FPGA-based hardware

    Multilevel Runtime Verification for Safety and Security Critical Cyber Physical Systems from a Model Based Engineering Perspective

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    Advanced embedded system technology is one of the key driving forces behind the rapid growth of Cyber-Physical System (CPS) applications. CPS consists of multiple coordinating and cooperating components, which are often software-intensive and interact with each other to achieve unprecedented tasks. Such highly integrated CPSs have complex interaction failures, attack surfaces, and attack vectors that we have to protect and secure against. This dissertation advances the state-of-the-art by developing a multilevel runtime monitoring approach for safety and security critical CPSs where there are monitors at each level of processing and integration. Given that computation and data processing vulnerabilities may exist at multiple levels in an embedded CPS, it follows that solutions present at the levels where the faults or vulnerabilities originate are beneficial in timely detection of anomalies. Further, increasing functional and architectural complexity of critical CPSs have significant safety and security operational implications. These challenges are leading to a need for new methods where there is a continuum between design time assurance and runtime or operational assurance. Towards this end, this dissertation explores Model Based Engineering methods by which design assurance can be carried forward to the runtime domain, creating a shared responsibility for reducing the overall risk associated with the system at operation. Therefore, a synergistic combination of Verification & Validation at design time and runtime monitoring at multiple levels is beneficial in assuring safety and security of critical CPS. Furthermore, we realize our multilevel runtime monitor framework on hardware using a stream-based runtime verification language

    A Survey on Security Threats and Countermeasures in IEEE Test Standards

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    International audienceEditor's note: Test infrastructure has been shown to be a portal for hackers. This article reviews the threats and countermeasures for IEEE test infrastructure standards

    Automated Debugging Methodology for FPGA-based Systems

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    Electronic devices make up a vital part of our lives. These are seen from mobiles, laptops, computers, home automation, etc. to name a few. The modern designs constitute billions of transistors. However, with this evolution, ensuring that the devices fulfill the designer’s expectation under variable conditions has also become a great challenge. This requires a lot of design time and effort. Whenever an error is encountered, the process is re-started. Hence, it is desired to minimize the number of spins required to achieve an error-free product, as each spin results in loss of time and effort. Software-based simulation systems present the main technique to ensure the verification of the design before fabrication. However, few design errors (bugs) are likely to escape the simulation process. Such bugs subsequently appear during the post-silicon phase. Finding such bugs is time-consuming due to inherent invisibility of the hardware. Instead of software simulation of the design in the pre-silicon phase, post-silicon techniques permit the designers to verify the functionality through the physical implementations of the design. The main benefit of the methodology is that the implemented design in the post-silicon phase runs many order-of-magnitude faster than its counterpart in pre-silicon. This allows the designers to validate their design more exhaustively. This thesis presents five main contributions to enable a fast and automated debugging solution for reconfigurable hardware. During the research work, we used an obstacle avoidance system for robotic vehicles as a use case to illustrate how to apply the proposed debugging solution in practical environments. The first contribution presents a debugging system capable of providing a lossless trace of debugging data which permits a cycle-accurate replay. This methodology ensures capturing permanent as well as intermittent errors in the implemented design. The contribution also describes a solution to enhance hardware observability. It is proposed to utilize processor-configurable concentration networks, employ debug data compression to transmit the data more efficiently, and partially reconfiguring the debugging system at run-time to save the time required for design re-compilation as well as preserve the timing closure. The second contribution presents a solution for communication-centric designs. Furthermore, solutions for designs with multi-clock domains are also discussed. The third contribution presents a priority-based signal selection methodology to identify the signals which can be more helpful during the debugging process. A connectivity generation tool is also presented which can map the identified signals to the debugging system. The fourth contribution presents an automated error detection solution which can help in capturing the permanent as well as intermittent errors without continuous monitoring of debugging data. The proposed solution works for designs even in the absence of golden reference. The fifth contribution proposes to use artificial intelligence for post-silicon debugging. We presented a novel idea of using a recurrent neural network for debugging when a golden reference is present for training the network. Furthermore, the idea was also extended to designs where golden reference is not present

    Reliable Design of Three-Dimensional Integrated Circuits

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    A dependable anisotropic magnetoresistance sensor system for automotive applications

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    The increasing usage of electronic systems in automotive applications aims to enhance passenger safety as well as the performance of the cars. In modern vehicles, the mechanical and hydraulic systems traditionally used have been replaced by X-by-wire systems in which the functions are performed by electronic components. However, the components required should be reliable, have a high-performance, low-cost and capable of operating for a long time in a highly dependable manner despite the harsh operating conditions in automotive applications. Dependability represents the reliance that a user justifiably poses on the service offered by a system, being this especially important in safety-critical applications in which a failure can constitute a threat to people or the environment. An Anisotropic Magnetoresistance (AMR) sensor is a type of magnetic sensor often used for angle measurements in cars. This sensor is affected by performance degradation and catastrophic faults that in principle cause the sensor to stop working suddenly. Therefore, the sensor dependability should be improved in order to guarantee that it will satisfy the continuous increasing dependability as well as accuracy requirements demanded by automotive applications. This research proposes an AMR sensor system that includes a fault-tolerant approach to handle catastrophic faults and self-X properties to maintain the performance of the sensor during its lifetime. Additionally, an interface with the IEEE 1687 standard has been considered, so the sensor is able to communicate with other components of the system in which it is integrated
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