Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields, including power electronics, illumination, and sensors. This reprint collects the 23 papers covering the full spectrum of the above applications and providing contributions from the on-going research at different levels, from materials to devices and from circuits to systems

Design, simulation, fabrication and characterisation of 4H-SiC trench MOSFETs

For solid-state power devices, there exists need for a material with a higher band gap which will result in a higher critical electric field, improved power efficiency and thermal performance. This has resulted in the use of Silicon Carbide (SiC) as a serious alternative to Silicon for power devices. SiC trench MOSFETs have attracted major attention in recent years because of 1) lower on resistance by eliminating the JFET effect which exists in lateral MOSFETs, 2) higher channel density which lowers the threshold voltage and 3) reduction of the required surface area because of the vertical channel. These advantages allow faster switching speeds and the potential for a higher density of devices leading to more compact modules. This work was focused on fabrication of the first generation of 4H-SiC trench MOSFETs in Warwick University. Two main goals were achieved in this work: a comprehensive understanding of fabrication of trenches in 4H-SiC and fabrication of first generation of 4H-SiC trench MOSFET with mobility as high as 3

Integration of Ferroelectric HfO2 onto a III-V Nanowire Platform

The discovery of ferroelectricity in CMOS-compatible oxides, such as doped hafnium oxide, has opened new possibilities for electronics by reviving the use of ferroelectric implementations on modern technology platforms. This thesis presents the ground-up integration of ferroelectric HfO2 on a thermally sensitive III-V nanowire platform leading to the successful implementation of ferroelectric transistors (FeFETs), tunnel junctions (FTJs), and varactors for mm-wave applications. As ferroelectric HfO2 on III-V semiconductors is a nascent technology, a special emphasis is put on the fundamental integration issues and the various engineering challenges facing the technology.The fabrication of metal-oxide-semiconductor (MOS) capacitors is treated as well as the measurement methods developed to investigate the interfacial quality to the narrow bandgap III-V materials using both electrical and operando synchrotron light source techniques. After optimizing both the films and the top electrode, the gate stack is integrated onto vertical InAs nanowires on Si in order to successfully implement FeFETs. Their performance and reliability can be explained from the deeper physical understanding obtained from the capacitor structures.By introducing an InAs/(In)GaAsSb/GaSb heterostructure in the nanowire, a ferroelectric tunnel field effect transistor (ferro-TFET) is fabricated. Based on the ultra-short effective channel created by the band-to-band tunneling process, the localized potential variations induced by single ultra-scaled ferroelectric domains and individual defects are sensed and investigated. By intentionally introducing a gate-source overlap in the ferro-TFET, a non-volatile reconfigurable single-transistor solution for modulating an input signal with diverse modes including signal transmission, phase shift, frequency doubling, and mixing is implemented.Finally, by fabricating scaled ferroelectric MOS capacitors in the front-end with a dedicated and adopted RF and mm-wave backend-of-line (BEOL) implementation, the ferroelectric behavior is captured at RF and mm-wave frequencies

Formation and characterization of n/p shallow junctions in sub-micron MOSFETs

Semiconductors are the burgeoning industries in today\u27s information age. Silicon based microelectronic devices are shrinking day-by-day in accord with the scaling dimensions reported by the International Technology Roadmap for Semiconductors (ITRS). There have been many semiconductor models and simulation programs constantly keeping pace with the continuously evolving scaling dimensions, process technology, performance and cost. Electrical characterization plays a vital role in determining the electrical properties of materials and device structures. Silicon based Metal Oxide Semiconductor Field Effect Transistor (MOSFET) forms the basis of Complimentary Metal Oxide Semiconductor (CMOS) circuits. Today\u27s aggressive scaling approaches in silicon Integrated Circuit (IC) technology require ultra shallow junctions in MOSFETs. The objective of this thesis is to study the leakage current in n/p shallow junctions and to correlate them with process steps required for the formation of shallow junctions. The leakage current measurements were performed by utilizing three-point probe method, which is one of the popular techniques used in the semiconductor industry. Apart from n/p shallow junctions, experiments have been performed on p/n shallow junctions. Finally, comparison of the leakage current measurements has been made. The comparison takes into account the implant variables and post-implant annealing steps that have been deployed in the fabrication of shallow junctions

Schottky source/drain transistor integrated with high-k and metal gate for sub-tenth nm technology

Ph.DDOCTOR OF PHILOSOPH

Non-Silicon MOSFETs and Circuits with Atomic Layer Deposited Higher-k Dielectrics

The quest for technologies beyond 14nm node complementary metal-oxide-semiconductor (CMOS) devices has now called for research on higher-k gate dielectrics integration with high mobility channel materials such as III-V semiconductors and germanium. Ternary oxides, such as La2-xYxO3 and LaAlO3, have been considered as strong candidates due to their high dielectric constants and good thermal stability. Meanwhile, the unique abilities of delivering large area uniform thin film, excellent controlling of composition and thickness to an atomic level, which are keys to ultra-scaled devices, have made atomic layer deposition (ALD) technique an excellent choice. In this thesis, we systematically study the atomic layer epitaxy (ALE) process realized by ALD, ALE higher-k dielectric integration, GaAs nMOSFETs and pMOSFETs on (111)A substrates, and their related CMOS digital logic gate circuits as well as ring oscillators. A record high drain current of 376 mA/mm and a small SS of 74 mV/dec are obtained from planar GaAs nMOSFETs with 1μm gate length. La2-xYxO3/GaAs(111)A interfaces are systematically investigated in both material and electrical aspects. The work has expanded the near 50 years GaAs MOSFETs research to an unprecedented level. Following the GaAs work, Ge n- and p-MOSFETs with epitaxial interfaces are also fabricated and studied. Beyond the conventional semiconductors, the complex oxide channel material SrTiO3 is also explored. Well-behaved LaAlO3/SrTiO3 nMOSFETs with a conducting channel at insulating ALD amorphous LaAlO3 - insulating crystalline SrTiO3 interface are also demonstrated

Editorial for the Special Issue on Wide Bandgap Based Devices: Design, Fabrication and Applications, Volume II

Wide bandgap (WBG) semiconductors are becoming a key enabling technology for several strategic fields of human activities [...]