A Low-Power and High-Speed Frequency Multiplier for DLL-Based Clock Generator

A low-power and high-speed frequency multiplier for a delay-locked loop-based clock generator is proposed to generate a multiplied clock with different range of frequencies. The modified edge combiner consumes low power and achieves a high-speed operation. The proposed frequency multiplier overcomes a deterministic jitter problem by reducing the delay difference between positive- and negative-edge generation paths. The proposed frequency multiplier is implemented in a 0.13-µm CMOS process technology achieved power consumption to a frequency ratio of 2.9 µW/MHz, and has the multiplication ratios of 16, and an output range of 100 MHz–3.3 GHz

Design of Low Power, High Speed Frequency Multiplier Based On DPLL for Clock Generation

A low-power and high-speed frequency multiplier for a DPLL-based clock generator is proposed to produce a multiplied clock with a high frequency and a greatest frequency rang. The proposed frequency multiplier devours low power and accomplishes a rapid activity. The proposed frequency multiplier minimizes the delay difference between the positive and negative edge generation paths. This is fabricated in a 0.12μm CMOS process technology and accomplished power utilization to a frequency ratio of 0.698mw, and it generates 59 phase differential clocksand has the maximum multiplication ratio of 33, and an output range of 100MHz